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https://github.com/brain-hackers/u-boot-brain
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52c411805c
It looks like only cm5200 and tqm8xx use this feature, so we don't really need it in generic code. Drop it and have the users access gd->board_type directly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
286 lines
6.7 KiB
C
286 lines
6.7 KiB
C
/*
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* (C) Copyright 2006
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <ioports.h>
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#include <mpc83xx.h>
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#include <asm/mpc8349_pci.h>
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#include <i2c.h>
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#include <spi.h>
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#include <miiphy.h>
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#ifdef CONFIG_SYS_FSL_DDR2
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#include <fsl_ddr_sdram.h>
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#else
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#include <spd_sdram.h>
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#endif
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#if defined(CONFIG_OF_LIBFDT)
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#include <libfdt.h>
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#endif
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int fixed_sdram(void);
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void sdram_init(void);
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#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx)
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void ddr_enable_ecc(unsigned int dram_size);
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#endif
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int board_early_init_f (void)
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{
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volatile u8* bcsr = (volatile u8*)CONFIG_SYS_BCSR;
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/* Enable flash write */
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bcsr[1] &= ~0x01;
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#ifdef CONFIG_SYS_USE_MPC834XSYS_USB_PHY
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/* Use USB PHY on SYS board */
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bcsr[5] |= 0x02;
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#endif
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return 0;
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}
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#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
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phys_size_t initdram(void)
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{
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volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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phys_size_t msize = 0;
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if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
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return -1;
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/* DDR SDRAM - Main SODIMM */
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im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
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#if defined(CONFIG_SPD_EEPROM)
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#ifndef CONFIG_SYS_FSL_DDR2
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msize = spd_sdram() * 1024 * 1024;
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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ddr_enable_ecc(msize);
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#endif
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#else
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msize = fsl_ddr_sdram();
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#endif
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#else
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msize = fixed_sdram() * 1024 * 1024;
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#endif
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/*
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* Initialize SDRAM if it is on local bus.
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*/
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sdram_init();
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/* return total bus SDRAM size(bytes) -- DDR */
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return msize;
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}
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#if !defined(CONFIG_SPD_EEPROM)
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/*************************************************************************
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* fixed sdram init -- doesn't use serial presence detect.
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************************************************************************/
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int fixed_sdram(void)
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{
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volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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u32 msize = CONFIG_SYS_DDR_SIZE;
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u32 ddr_size = msize << 20; /* DDR size in bytes */
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u32 ddr_size_log2 = __ilog2(ddr_size);
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im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
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im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
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#if (CONFIG_SYS_DDR_SIZE != 256)
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#warning Currenly any ddr size other than 256 is not supported
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#endif
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#ifdef CONFIG_DDR_II
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im->ddr.csbnds[2].csbnds = CONFIG_SYS_DDR_CS2_BNDS;
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im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
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im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
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im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
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im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
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im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
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im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
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im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
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im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
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im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
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im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
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im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
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#else
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#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
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#warning Chip select bounds is only configurable in 16MB increments
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#endif
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im->ddr.csbnds[2].csbnds =
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((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
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(((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
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CSBNDS_EA_SHIFT) & CSBNDS_EA);
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im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
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/* currently we use only one CS, so disable the other banks */
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im->ddr.cs_config[0] = 0;
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im->ddr.cs_config[1] = 0;
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im->ddr.cs_config[3] = 0;
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im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
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im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
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im->ddr.sdram_cfg =
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SDRAM_CFG_SREN
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#if defined(CONFIG_DDR_2T_TIMING)
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| SDRAM_CFG_2T_EN
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#endif
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| 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
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#if defined (CONFIG_DDR_32BIT)
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/* for 32-bit mode burst length is 8 */
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im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
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#endif
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im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
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im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
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#endif
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udelay(200);
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/* enable DDR controller */
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im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
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return msize;
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}
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#endif/*!CONFIG_SYS_SPD_EEPROM*/
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int checkboard (void)
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{
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/*
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* Warning: do not read the BCSR registers here
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*
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* There is a timing bug in the 8349E and 8349EA BCSR code
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* version 1.2 (read from BCSR 11) that will cause the CFI
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* flash initialization code to overwrite BCSR 0, disabling
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* the serial ports and gigabit ethernet
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*/
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puts("Board: Freescale MPC8349EMDS\n");
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return 0;
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}
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/*
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* if MPC8349EMDS is soldered with SDRAM
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*/
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#if defined(CONFIG_SYS_BR2_PRELIM) \
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&& defined(CONFIG_SYS_OR2_PRELIM) \
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&& defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
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&& defined(CONFIG_SYS_LBLAWAR2_PRELIM)
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/*
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* Initialize SDRAM memory on the Local Bus.
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*/
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void sdram_init(void)
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{
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volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
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volatile fsl_lbc_t *lbc = &immap->im_lbc;
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uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
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/*
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* Setup SDRAM Base and Option Registers, already done in cpu_init.c
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*/
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/* setup mtrpt, lsrt and lbcr for LB bus */
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lbc->lbcr = CONFIG_SYS_LBC_LBCR;
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lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
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lbc->lsrt = CONFIG_SYS_LBC_LSRT;
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asm("sync");
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/*
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* Configure the SDRAM controller Machine Mode Register.
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*/
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lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
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lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
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asm("sync");
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*sdram_addr = 0xff;
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udelay(100);
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lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */
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asm("sync");
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/*1 times*/
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*sdram_addr = 0xff;
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udelay(100);
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/*2 times*/
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*sdram_addr = 0xff;
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udelay(100);
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/*3 times*/
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*sdram_addr = 0xff;
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udelay(100);
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/*4 times*/
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*sdram_addr = 0xff;
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udelay(100);
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/*5 times*/
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*sdram_addr = 0xff;
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udelay(100);
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/*6 times*/
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*sdram_addr = 0xff;
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udelay(100);
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/*7 times*/
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*sdram_addr = 0xff;
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udelay(100);
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/*8 times*/
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*sdram_addr = 0xff;
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udelay(100);
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/* 0x58636733; mode register write operation */
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lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
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asm("sync");
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*sdram_addr = 0xff;
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udelay(100);
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lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
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asm("sync");
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*sdram_addr = 0xff;
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udelay(100);
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}
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#else
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void sdram_init(void)
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{
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}
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#endif
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/*
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* The following are used to control the SPI chip selects for the SPI command.
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*/
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#ifdef CONFIG_MPC8XXX_SPI
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#define SPI_CS_MASK 0x80000000
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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{
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return bus == 0 && cs == 0;
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}
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void spi_cs_activate(struct spi_slave *slave)
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{
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volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
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iopd->dat &= ~SPI_CS_MASK;
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}
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void spi_cs_deactivate(struct spi_slave *slave)
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{
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volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
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iopd->dat |= SPI_CS_MASK;
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}
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#endif /* CONFIG_HARD_SPI */
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#if defined(CONFIG_OF_BOARD_SETUP)
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int ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
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#ifdef CONFIG_PCI
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ft_pci_setup(blob, bd);
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#endif
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return 0;
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}
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#endif
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