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![Patrice Chotard](/assets/img/avatar_default.png)
Add STMicroelectronics STiH410 pinctrl driver Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
321 lines
7.7 KiB
C
321 lines
7.7 KiB
C
/*
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* Pinctrl driver for STMicroelectronics STi SoCs
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*
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* Copyright (c) 2017
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* Patrice Chotard <patrice.chotard@st.com>
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <bitfield.h>
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#include <dm.h>
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#include <errno.h>
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#include <regmap.h>
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#include <syscon.h>
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#include <asm/io.h>
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#include <dm/pinctrl.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define MAX_STI_PINCONF_ENTRIES 7
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/* Output enable */
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#define OE (1 << 27)
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/* Pull Up */
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#define PU (1 << 26)
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/* Open Drain */
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#define OD (1 << 25)
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/* User-frendly defines for Pin Direction */
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/* oe = 0, pu = 0, od = 0 */
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#define IN (0)
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/* oe = 0, pu = 1, od = 0 */
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#define IN_PU (PU)
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/* oe = 1, pu = 0, od = 0 */
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#define OUT (OE)
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/* oe = 1, pu = 1, od = 0 */
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#define OUT_PU (OE | PU)
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/* oe = 1, pu = 0, od = 1 */
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#define BIDIR (OE | OD)
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/* oe = 1, pu = 1, od = 1 */
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#define BIDIR_PU (OE | PU | OD)
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struct sti_pinctrl_platdata {
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struct regmap *regmap;
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};
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struct sti_pin_desc {
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unsigned char bank;
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unsigned char pin;
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unsigned char alt;
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int dir;
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};
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/*
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* PIO alternative Function selector
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*/
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void sti_alternate_select(struct udevice *dev, struct sti_pin_desc *pin_desc)
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{
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struct sti_pinctrl_platdata *plat = dev_get_platdata(dev);
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unsigned long sysconf, *sysconfreg;
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int alt = pin_desc->alt;
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int bank = pin_desc->bank;
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int pin = pin_desc->pin;
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sysconfreg = (unsigned long *)plat->regmap->base;
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switch (bank) {
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case 0 ... 5: /* in "SBC Bank" */
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sysconfreg += bank;
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break;
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case 10 ... 20: /* in "FRONT Bank" */
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sysconfreg += bank - 10;
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break;
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case 30 ... 35: /* in "REAR Bank" */
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sysconfreg += bank - 30;
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break;
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case 40 ... 42: /* in "FLASH Bank" */
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sysconfreg += bank - 40;
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break;
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default:
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BUG();
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return;
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}
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sysconf = readl(sysconfreg);
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sysconf = bitfield_replace(sysconf, pin * 4, 3, alt);
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writel(sysconf, sysconfreg);
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}
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/* pin configuration */
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void sti_pin_configure(struct udevice *dev, struct sti_pin_desc *pin_desc)
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{
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struct sti_pinctrl_platdata *plat = dev_get_platdata(dev);
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int bit;
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int oe = 0, pu = 0, od = 0;
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unsigned long *sysconfreg;
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int bank = pin_desc->bank;
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sysconfreg = (unsigned long *)plat->regmap->base + 40;
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/*
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* NOTE: The PIO configuration for the PIO pins in the
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* "FLASH Bank" are different from all the other banks!
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* Specifically, the output-enable pin control register
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* (SYS_CFG_3040) and the pull-up pin control register
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* (SYS_CFG_3050), are both classed as being "reserved".
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* Hence, we do not write to these registers to configure
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* the OE and PU features for PIOs in this bank. However,
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* the open-drain pin control register (SYS_CFG_3060)
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* follows the style of the other banks, and so we can
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* treat that register normally.
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*
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* Being pedantic, we should configure the PU and PD features
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* in the "FLASH Bank" explicitly instead using the four
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* SYS_CFG registers: 3080, 3081, 3085, and 3086. However, this
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* would necessitate passing in the alternate function number
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* to this function, and adding some horrible complexity here.
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* Alternatively, we could just perform 4 32-bit "pokes" to
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* these four SYS_CFG registers early in the initialization.
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* In practice, these four SYS_CFG registers are correct
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* after a reset, and U-Boot does not need to change them, so
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* we (cheat and) rely on these registers being correct.
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* WARNING: Please be aware of this (pragmatic) behaviour!
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*/
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int flashss = 0; /* bool: PIO in the Flash Sub-System ? */
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switch (pin_desc->dir) {
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case IN:
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oe = 0; pu = 0; od = 0;
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break;
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case IN_PU:
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oe = 0; pu = 1; od = 0;
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break;
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case OUT:
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oe = 1; pu = 0; od = 0;
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break;
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case BIDIR:
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oe = 1; pu = 0; od = 1;
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break;
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case BIDIR_PU:
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oe = 1; pu = 1; od = 1;
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break;
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default:
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error("%s invalid direction value: 0x%x\n",
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__func__, pin_desc->dir);
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BUG();
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break;
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}
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switch (bank) {
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case 0 ... 5: /* in "SBC Bank" */
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sysconfreg += bank / 4;
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break;
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case 10 ... 20: /* in "FRONT Bank" */
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bank -= 10;
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sysconfreg += bank / 4;
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break;
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case 30 ... 35: /* in "REAR Bank" */
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bank -= 30;
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sysconfreg += bank / 4;
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break;
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case 40 ... 42: /* in "FLASH Bank" */
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bank -= 40;
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sysconfreg += bank / 4;
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flashss = 1; /* pin is in the Flash Sub-System */
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break;
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default:
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BUG();
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return;
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}
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bit = ((bank * 8) + pin_desc->pin) % 32;
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/*
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* set the "Output Enable" pin control
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* but, do nothing if in the flashSS
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*/
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if (!flashss) {
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if (oe)
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generic_set_bit(bit, sysconfreg);
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else
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generic_clear_bit(bit, sysconfreg);
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}
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sysconfreg += 10; /* skip to next set of syscfg registers */
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/*
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* set the "Pull Up" pin control
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* but, do nothing if in the FlashSS
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*/
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if (!flashss) {
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if (pu)
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generic_set_bit(bit, sysconfreg);
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else
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generic_clear_bit(bit, sysconfreg);
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}
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sysconfreg += 10; /* skip to next set of syscfg registers */
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/* set the "Open Drain Enable" pin control */
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if (od)
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generic_set_bit(bit, sysconfreg);
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else
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generic_clear_bit(bit, sysconfreg);
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}
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static int sti_pinctrl_set_state(struct udevice *dev, struct udevice *config)
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{
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struct fdtdec_phandle_args args;
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const void *blob = gd->fdt_blob;
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const char *prop_name;
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int node = dev_of_offset(config);
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int property_offset, prop_len;
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int pinconf_node, ret, count;
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const char *bank_name;
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u32 cells[MAX_STI_PINCONF_ENTRIES];
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struct sti_pin_desc pin_desc;
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/* go to next node "st,pins" which contains the pins configuration */
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pinconf_node = fdt_subnode_offset(blob, node, "st,pins");
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/*
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* parse each pins configuration which looks like :
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* pin_name = <bank_phandle pin_nb alt dir rt_type rt_delay rt_clk>
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*/
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fdt_for_each_property_offset(property_offset, blob, pinconf_node) {
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fdt_getprop_by_offset(blob, property_offset, &prop_name,
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&prop_len);
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/* extract the bank of the pin description */
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ret = fdtdec_parse_phandle_with_args(blob, pinconf_node,
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prop_name, "#gpio-cells",
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0, 0, &args);
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if (ret < 0) {
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error("Can't get the gpio bank phandle: %d\n", ret);
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return ret;
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}
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bank_name = fdt_getprop(blob, args.node, "st,bank-name",
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&count);
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if (count < 0) {
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error("Can't find bank-name property %d\n", count);
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return -EINVAL;
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}
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pin_desc.bank = trailing_strtoln(bank_name, NULL);
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count = fdtdec_get_int_array_count(blob, pinconf_node,
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prop_name, cells,
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ARRAY_SIZE(cells));
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if (count < 0) {
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error("Bad pin configuration array %d\n", count);
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return -EINVAL;
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}
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if (count > MAX_STI_PINCONF_ENTRIES) {
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error("Unsupported pinconf array count %d\n", count);
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return -EINVAL;
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}
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pin_desc.pin = cells[1];
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pin_desc.alt = cells[2];
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pin_desc.dir = cells[3];
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sti_alternate_select(dev, &pin_desc);
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sti_pin_configure(dev, &pin_desc);
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};
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return 0;
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}
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static int sti_pinctrl_probe(struct udevice *dev)
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{
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struct sti_pinctrl_platdata *plat = dev_get_platdata(dev);
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struct udevice *syscon;
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int err;
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/* get corresponding syscon phandle */
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err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
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"st,syscfg", &syscon);
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if (err) {
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error("unable to find syscon device\n");
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return err;
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}
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plat->regmap = syscon_get_regmap(syscon);
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if (!plat->regmap) {
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error("unable to find regmap\n");
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return -ENODEV;
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}
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return 0;
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}
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static const struct udevice_id sti_pinctrl_ids[] = {
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{ .compatible = "st,stih407-sbc-pinctrl" },
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{ .compatible = "st,stih407-front-pinctrl" },
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{ .compatible = "st,stih407-rear-pinctrl" },
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{ .compatible = "st,stih407-flash-pinctrl" },
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{ }
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};
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const struct pinctrl_ops sti_pinctrl_ops = {
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.set_state = sti_pinctrl_set_state,
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};
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U_BOOT_DRIVER(pinctrl_sti) = {
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.name = "pinctrl_sti",
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.id = UCLASS_PINCTRL,
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.of_match = sti_pinctrl_ids,
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.ops = &sti_pinctrl_ops,
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.probe = sti_pinctrl_probe,
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.platdata_auto_alloc_size = sizeof(struct sti_pinctrl_platdata),
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.ops = &sti_pinctrl_ops,
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};
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