mirror of
https://github.com/brain-hackers/u-boot-brain
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7bcdd0c1f8
Pull out the GIC macros from the board configuration files into the common Gen3 configuration file since these macros are the same for all Gen3 systems. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
95 lines
2.4 KiB
C
95 lines
2.4 KiB
C
/*
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* include/configs/ulcb.h
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* This file is ULCB board configuration.
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*
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* Copyright (C) 2017 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ULCB_H
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#define __ULCB_H
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#undef DEBUG
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#define CONFIG_RCAR_BOARD_STRING "ULCB"
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#include "rcar-gen3-common.h"
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/* M3 ULCB has 2 banks, each with 1 GiB of RAM */
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#if defined(CONFIG_R8A7796)
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#undef PHYS_SDRAM_1_SIZE
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#undef PHYS_SDRAM_2_SIZE
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#define PHYS_SDRAM_1_SIZE (0x40000000u - DRAM_RSV_SIZE)
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#define PHYS_SDRAM_2_SIZE 0x40000000u
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#endif
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/* SCIF */
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#define CONFIG_CONS_SCIF2
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#define CONFIG_CONS_INDEX 2
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#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_S3D4_CLK_FREQ
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/* [A] Hyper Flash */
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/* use to RPC(SPI Multi I/O Bus Controller) */
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/* Ethernet RAVB */
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#define CONFIG_BITBANGMII
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#define CONFIG_BITBANGMII_MULTI
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/* Board Clock */
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/* XTAL_CLK : 33.33MHz */
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#define RCAR_XTAL_CLK 33333333u
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#define CONFIG_SYS_CLK_FREQ RCAR_XTAL_CLK
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/* ch0to2 CPclk, ch3to11 S3D2_PEREclk, ch12to14 S3D2_RTclk */
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/* CPclk 16.66MHz, S3D2 133.33MHz , S3D4 66.66MHz */
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#define CONFIG_CP_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
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#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 192 / 2)
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#define CONFIG_S3D2_CLK_FREQ (266666666u/2)
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#define CONFIG_S3D4_CLK_FREQ (266666666u/4)
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/* Generic Timer Definitions (use in assembler source) */
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#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */
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/* CPLD SPI */
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#define CONFIG_CMD_SPI
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#define CONFIG_SOFT_SPI
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#define SPI_DELAY udelay(0)
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#define SPI_SDA(val) ulcb_softspi_sda(val)
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#define SPI_SCL(val) ulcb_softspi_scl(val)
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#define SPI_READ ulcb_softspi_read()
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#ifndef __ASSEMBLY__
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void ulcb_softspi_sda(int);
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void ulcb_softspi_scl(int);
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unsigned char ulcb_softspi_read(void);
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#endif
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/* i2c */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_SH
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#define CONFIG_SYS_I2C_SLAVE 0x60
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#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 1
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#define CONFIG_SYS_I2C_SH_SPEED0 400000
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#define CONFIG_SH_I2C_DATA_HIGH 4
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#define CONFIG_SH_I2C_DATA_LOW 5
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#define CONFIG_SH_I2C_CLOCK 10000000
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#define CONFIG_SYS_I2C_POWERIC_ADDR 0x30
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/* SDHI */
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#define CONFIG_SH_SDHI_FREQ 200000000
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/* Environment in eMMC, at the end of 2nd "boot sector" */
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#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
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#define CONFIG_SYS_MMC_ENV_DEV 1
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#define CONFIG_SYS_MMC_ENV_PART 2
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/* Module stop status bits */
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/* MFIS, SCIF1 */
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#define CONFIG_SMSTP2_ENA 0x00002040
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/* SCIF2 */
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#define CONFIG_SMSTP3_ENA 0x00000400
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/* INTC-AP, IRQC */
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#define CONFIG_SMSTP4_ENA 0x00000180
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#endif /* __ULCB_H */
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