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https://github.com/brain-hackers/u-boot-brain
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52568c3654
ARIA is a MPC5121E based COM Express module by Dave/DENX. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: John Rigby <jcrigby@gmail.com>
317 lines
10 KiB
C
317 lines
10 KiB
C
/*
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* (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
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* (C) Copyright 2009 Dave Srl www.dave.eu
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#include <asm/bitops.h>
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#include <command.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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#include <fdt_support.h>
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#ifdef CONFIG_MISC_INIT_R
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#include <i2c.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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extern int mpc5121_diu_init(void);
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extern void ide_set_reset(int idereset);
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/* Clocks in use */
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#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
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CLOCK_SCCR1_LPC_EN | \
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CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
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CLOCK_SCCR1_PSCFIFO_EN | \
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CLOCK_SCCR1_DDR_EN | \
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CLOCK_SCCR1_FEC_EN | \
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CLOCK_SCCR1_PATA_EN | \
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CLOCK_SCCR1_PCI_EN | \
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CLOCK_SCCR1_TPR_EN)
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#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
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CLOCK_SCCR2_SPDIF_EN | \
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CLOCK_SCCR2_DIU_EN | \
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CLOCK_SCCR2_I2C_EN)
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#define CSAW_START(start) ((start) & 0xFFFF0000)
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#define CSAW_STOP(start, size) (((start) + (size) - 1) >> 16)
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long int fixed_sdram(void);
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int board_early_init_f(void)
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{
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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u32 spridr;
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/*
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* Initialize Local Window for the On Board FPGA access
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*/
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out_be32(&im->sysconf.lpcs2aw,
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CSAW_START(CONFIG_SYS_ARIA_FPGA_BASE) |
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CSAW_STOP(CONFIG_SYS_ARIA_FPGA_BASE, CONFIG_SYS_ARIA_FPGA_SIZE)
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);
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out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG);
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/*
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* According to MPC5121e RM, configuring local access windows should
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* be followed by a dummy read of the config register that was
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* modified last and an isync
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*/
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in_be32(&im->sysconf.lpcs2aw);
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__asm__ __volatile__ ("isync");
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/*
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* Initialize Local Window for the On Board SRAM access
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*/
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out_be32(&im->sysconf.lpcs6aw,
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CSAW_START(CONFIG_SYS_ARIA_SRAM_BASE) |
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CSAW_STOP(CONFIG_SYS_ARIA_SRAM_BASE, CONFIG_SYS_ARIA_SRAM_SIZE)
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);
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out_be32(&im->lpc.cs_cfg[6], CONFIG_SYS_CS6_CFG);
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/*
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* According to MPC5121e RM, configuring local access windows should
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* be followed by a dummy read of the config register that was
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* modified last and an isync
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*/
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in_be32(&im->sysconf.lpcs6aw);
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__asm__ __volatile__ ("isync");
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/*
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* Configure Flash Speed
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*/
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out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG);
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spridr = in_be32(&im->sysconf.spridr);
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if (SVR_MJREV(spridr) >= 2)
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out_be32(&im->lpc.altr, CONFIG_SYS_CS_ALETIMING);
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/*
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* Enable clocks
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*/
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out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN);
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out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN);
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#if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
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setbits_be32(&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN);
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#endif
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return 0;
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}
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phys_size_t initdram (int board_type)
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{
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return fixed_sdram();
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}
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/*
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* fixed sdram init:
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* The board doesn't use memory modules that have serial presence
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* detect or similar mechanism for discovery of the DRAM settings
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*/
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long int fixed_sdram (void)
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{
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
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u32 msize_log2 = __ilog2(msize);
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u32 i;
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/* Initialize IO Control */
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out_be32(&im->io_ctrl.io_control_mem, IOCTRL_MUX_DDR);
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/* Initialize DDR Local Window */
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out_be32(&im->sysconf.ddrlaw.bar, CONFIG_SYS_DDR_BASE & 0xFFFFF000);
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out_be32(&im->sysconf.ddrlaw.ar, msize_log2 - 1);
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/*
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* According to MPC5121e RM, configuring local access windows should
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* be followed by a dummy read of the config register that was
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* modified last and an isync
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*/
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in_be32(&im->sysconf.ddrlaw.ar);
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__asm__ __volatile__ ("isync");
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/* Enable DDR */
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out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_EN);
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/* Initialize DDR Priority Manager */
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out_be32(&im->mddrc.prioman_config1, CONFIG_SYS_MDDRCGRP_PM_CFG1);
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out_be32(&im->mddrc.prioman_config2, CONFIG_SYS_MDDRCGRP_PM_CFG2);
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out_be32(&im->mddrc.hiprio_config, CONFIG_SYS_MDDRCGRP_HIPRIO_CFG);
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out_be32(&im->mddrc.lut_table0_main_upper, CONFIG_SYS_MDDRCGRP_LUT0_MU);
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out_be32(&im->mddrc.lut_table0_main_lower, CONFIG_SYS_MDDRCGRP_LUT0_ML);
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out_be32(&im->mddrc.lut_table1_main_upper, CONFIG_SYS_MDDRCGRP_LUT1_MU);
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out_be32(&im->mddrc.lut_table1_main_lower, CONFIG_SYS_MDDRCGRP_LUT1_ML);
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out_be32(&im->mddrc.lut_table2_main_upper, CONFIG_SYS_MDDRCGRP_LUT2_MU);
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out_be32(&im->mddrc.lut_table2_main_lower, CONFIG_SYS_MDDRCGRP_LUT2_ML);
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out_be32(&im->mddrc.lut_table3_main_upper, CONFIG_SYS_MDDRCGRP_LUT3_MU);
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out_be32(&im->mddrc.lut_table3_main_lower, CONFIG_SYS_MDDRCGRP_LUT3_ML);
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out_be32(&im->mddrc.lut_table4_main_upper, CONFIG_SYS_MDDRCGRP_LUT4_MU);
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out_be32(&im->mddrc.lut_table4_main_lower, CONFIG_SYS_MDDRCGRP_LUT4_ML);
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out_be32(&im->mddrc.lut_table0_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT0_AU);
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out_be32(&im->mddrc.lut_table0_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT0_AL);
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out_be32(&im->mddrc.lut_table1_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT1_AU);
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out_be32(&im->mddrc.lut_table1_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT1_AL);
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out_be32(&im->mddrc.lut_table2_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT2_AU);
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out_be32(&im->mddrc.lut_table2_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT2_AL);
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out_be32(&im->mddrc.lut_table3_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT3_AU);
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out_be32(&im->mddrc.lut_table3_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT3_AL);
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out_be32(&im->mddrc.lut_table4_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT4_AU);
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out_be32(&im->mddrc.lut_table4_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT4_AL);
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/* Initialize MDDRC */
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out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG);
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out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0);
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out_be32(&im->mddrc.ddr_time_config1, CONFIG_SYS_MDDRC_TIME_CFG1);
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out_be32(&im->mddrc.ddr_time_config2, CONFIG_SYS_MDDRC_TIME_CFG2);
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/* Initialize DDR */
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for (i = 0; i < 10; i++)
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM3);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EN_DLL);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_OCD_DEFAULT);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
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out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
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/* Start MDDRC */
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out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0_RUN);
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out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_RUN);
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return msize;
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}
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int misc_init_r(void)
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{
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u32 tmp;
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/* we use I2C-2 for on-board eeprom */
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i2c_set_bus_num(2);
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tmp = in_be32((u32*)CONFIG_SYS_ARIA_FPGA_BASE);
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printf("FPGA: %u-%u.%u.%u\n",
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(tmp & 0xFF000000) >> 24,
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(tmp & 0x00FF0000) >> 16,
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(tmp & 0x0000FF00) >> 8,
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tmp & 0x000000FF
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);
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#ifdef CONFIG_FSL_DIU_FB
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# if !(defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE))
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mpc5121_diu_init();
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# endif
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#endif
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return 0;
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}
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static iopin_t ioregs_init[] = {
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/*
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* FEC
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*/
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/* FEC on PSCx_x*/
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{
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offsetof(struct ioctrl512x, io_control_psc0_0), 5, 0,
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IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
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},
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{
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offsetof(struct ioctrl512x, io_control_psc1_0), 10, 0,
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IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
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},
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{
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offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
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IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
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},
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/*
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* DIU
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*/
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/* FUNC2=DIU CLK */
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{
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offsetof(struct ioctrl512x, io_control_psc6_0), 1, 0,
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IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
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},
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/* FUNC2=DIU_HSYNC */
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{
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offsetof(struct ioctrl512x, io_control_psc6_1), 1, 0,
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IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
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},
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/* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
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{
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offsetof(struct ioctrl512x, io_control_psc6_4), 26, 0,
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IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
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},
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/*
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* On board SRAM
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*/
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/* FUNC2=/LPC CS6 */
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{
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offsetof(struct ioctrl512x, io_control_j1850_rx), 1, 0,
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IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(1) | IO_PIN_ST(1) | IO_PIN_DS(3)
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},
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};
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int checkboard (void)
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{
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puts("Board: ARIA\n");
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/* initialize function mux & slew rate IO inter alia on IO Pins */
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iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
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return 0;
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}
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#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
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void ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
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fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
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}
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#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
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