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![Przemyslaw Marczak](/assets/img/avatar_default.png)
This commit adds additional file with implementation of board detection code for Odroid-XU3/XU4. The detection depends on compatible found in fdt: - "samsung,exynos5" - uses Exynos5 generic code - "samsung,odroidxu3" - try detect XU3 revision There are few revisions of Odroid XU3/XU4, each can be detected by checking the value of channel 9 of built-in ADC: Rev ADC Board 0.1 0 XU3 0.1 0.2 372 XU3 0.2 | XU3L - no DISPLAYPORT 0.3 1280 XU4 0.1 The detection code depends on the ADC+10% value. Implementation of functions: - set_board_type() - read ADC and set type - get_board_rev() - returns board revision: 1..3 - get_board_type() - returns board type string Additional functions with return values of bool: - board_is_generic() - true if found compatible "samsung,exynos5" but not "samsung,odroidxu3" - board_is_odroidxu3() - true if found compatible "samsung,odroidxu3" and one of XU3 revision. - board_is_odroidxu4() - true if found compatible "samsung,odroidxu3" and XU4 revision. After I2C controller init, the get_board_type() can check if the XU3 board is a "Lite" variant, by probing chip 0x40 on I2C0 (INA231 - exists only on non-lite). This is useful for setting fdt file name at misc_init_r(). Enabled configs: - CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - CONFIG_ODROID_REV_AIN - CONFIG_REVISION_TAG - CONFIG_BOARD_TYPES Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Simon Glass <sjg@chromium.org> Tested-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
376 lines
8.0 KiB
C
376 lines
8.0 KiB
C
/*
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* Copyright (C) 2012 Samsung Electronics
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <dwc3-uboot.h>
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#include <fdtdec.h>
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#include <asm/io.h>
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#include <errno.h>
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#include <i2c.h>
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#include <mmc.h>
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#include <netdev.h>
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#include <samsung-usb-phy-uboot.h>
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#include <spi.h>
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#include <usb.h>
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#include <video_bridge.h>
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#include <asm/gpio.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/dwmmc.h>
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#include <asm/arch/mmc.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch/power.h>
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#include <asm/arch/sromc.h>
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#include <power/pmic.h>
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#include <power/max77686_pmic.h>
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#include <power/regulator.h>
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#include <power/s2mps11.h>
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#include <power/s5m8767.h>
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#include <samsung/exynos5-dt-types.h>
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#include <samsung/misc.h>
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#include <tmu.h>
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DECLARE_GLOBAL_DATA_PTR;
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static void board_enable_audio_codec(void)
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{
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int node, ret;
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struct gpio_desc en_gpio;
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node = fdtdec_next_compatible(gd->fdt_blob, 0,
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COMPAT_SAMSUNG_EXYNOS5_SOUND);
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if (node <= 0)
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return;
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ret = gpio_request_by_name_nodev(gd->fdt_blob, node,
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"codec-enable-gpio", 0, &en_gpio,
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GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
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if (ret == -FDT_ERR_NOTFOUND)
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return;
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/* Turn on the GPIO which connects to the codec's "enable" line. */
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gpio_set_pull(gpio_get_number(&en_gpio), S5P_GPIO_PULL_NONE);
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#ifdef CONFIG_SOUND_MAX98095
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/* Enable MAX98095 Codec */
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gpio_request(EXYNOS5_GPIO_X17, "max98095_enable");
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gpio_direction_output(EXYNOS5_GPIO_X17, 1);
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gpio_set_pull(EXYNOS5_GPIO_X17, S5P_GPIO_PULL_NONE);
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#endif
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}
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int exynos_init(void)
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{
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board_enable_audio_codec();
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return 0;
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}
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static int exynos_set_regulator(const char *name, uint uv)
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{
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struct udevice *dev;
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int ret;
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ret = regulator_get_by_platname(name, &dev);
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if (ret) {
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debug("%s: Cannot find regulator %s\n", __func__, name);
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return ret;
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}
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ret = regulator_set_value(dev, uv);
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if (ret) {
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debug("%s: Cannot set regulator %s\n", __func__, name);
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return ret;
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}
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return 0;
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}
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int exynos_power_init(void)
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{
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struct udevice *dev;
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int ret;
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ret = pmic_get("max77686", &dev);
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if (!ret) {
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/* TODO(sjg@chromium.org): Move into the clock/pmic API */
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ret = pmic_clrsetbits(dev, MAX77686_REG_PMIC_32KHZ, 0,
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MAX77686_32KHCP_EN);
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if (ret)
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return ret;
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ret = pmic_clrsetbits(dev, MAX77686_REG_PMIC_BBAT, 0,
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MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V);
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if (ret)
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return ret;
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} else {
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ret = pmic_get("s5m8767-pmic", &dev);
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/* TODO(sjg@chromium.org): Use driver model to access clock */
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#ifdef CONFIG_PMIC_S5M8767
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if (!ret)
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s5m8767_enable_32khz_cp(dev);
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#endif
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}
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if (ret == -ENODEV)
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return 0;
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ret = regulators_enable_boot_on(false);
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if (ret)
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return ret;
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ret = exynos_set_regulator("vdd_mif", 1100000);
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if (ret)
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return ret;
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/*
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* This would normally be 1.3V, but since we are running slowly 1.1V
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* is enough. For spring it helps reduce CPU temperature and avoid
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* hangs with the case open. 1.1V is minimum voltage borderline for
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* chained bootloaders.
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*/
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ret = exynos_set_regulator("vdd_arm", 1100000);
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if (ret)
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return ret;
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ret = exynos_set_regulator("vdd_int", 1012500);
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if (ret)
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return ret;
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ret = exynos_set_regulator("vdd_g3d", 1200000);
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if (ret)
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return ret;
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return 0;
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}
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int board_get_revision(void)
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{
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return 0;
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}
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#ifdef CONFIG_LCD
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static int board_dp_bridge_init(struct udevice *dev)
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{
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const int max_tries = 10;
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int num_tries;
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int ret;
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debug("%s\n", __func__);
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ret = video_bridge_attach(dev);
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if (ret) {
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debug("video bridge init failed: %d\n", ret);
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return ret;
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}
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/*
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* We need to wait for 90ms after bringing up the bridge since there
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* is a phantom "high" on the HPD chip during its bootup. The phantom
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* high comes within 7ms of de-asserting PD and persists for at least
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* 15ms. The real high comes roughly 50ms after PD is de-asserted. The
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* phantom high makes it hard for us to know when the NXP chip is up.
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*/
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mdelay(90);
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for (num_tries = 0; num_tries < max_tries; num_tries++) {
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/* Check HPD. If it's high, or we don't have it, all is well */
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ret = video_bridge_check_attached(dev);
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if (!ret || ret == -ENOENT)
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return 0;
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debug("%s: eDP bridge failed to come up; try %d of %d\n",
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__func__, num_tries, max_tries);
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}
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/* Immediately go into bridge reset if the hp line is not high */
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return -EIO;
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}
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static int board_dp_bridge_setup(const void *blob)
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{
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const int max_tries = 2;
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int num_tries;
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struct udevice *dev;
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int ret;
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/* Configure I2C registers for Parade bridge */
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ret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, &dev);
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if (ret) {
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debug("video bridge init failed: %d\n", ret);
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return ret;
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}
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if (strncmp(dev->driver->name, "parade", 6)) {
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/* Mux HPHPD to the special hotplug detect mode */
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exynos_pinmux_config(PERIPH_ID_DPHPD, 0);
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}
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for (num_tries = 0; num_tries < max_tries; num_tries++) {
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ret = board_dp_bridge_init(dev);
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if (!ret)
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return 0;
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if (num_tries == max_tries - 1)
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break;
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/*
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* If we're here, the bridge chip failed to initialise.
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* Power down the bridge in an attempt to reset.
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*/
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video_bridge_set_active(dev, false);
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/*
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* Arbitrarily wait 300ms here with DP_N low. Don't know for
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* sure how long we should wait, but we're being paranoid.
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*/
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mdelay(300);
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}
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return ret;
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}
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void exynos_cfg_lcd_gpio(void)
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{
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/* For Backlight */
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gpio_request(EXYNOS5_GPIO_B20, "lcd_backlight");
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gpio_cfg_pin(EXYNOS5_GPIO_B20, S5P_GPIO_OUTPUT);
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gpio_set_value(EXYNOS5_GPIO_B20, 1);
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}
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void exynos_set_dp_phy(unsigned int onoff)
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{
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set_dp_phy_ctrl(onoff);
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}
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static int board_dp_set_backlight(int percent)
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{
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struct udevice *dev;
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int ret;
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ret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, &dev);
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if (!ret)
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ret = video_bridge_set_backlight(dev, percent);
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return ret;
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}
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void exynos_backlight_on(unsigned int on)
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{
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struct udevice *dev;
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int ret;
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debug("%s(%u)\n", __func__, on);
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if (!on)
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return;
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ret = regulator_get_by_platname("vcd_led", &dev);
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if (!ret)
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ret = regulator_set_enable(dev, true);
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if (ret)
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debug("Failed to enable backlight: ret=%d\n", ret);
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/* T5 in the LCD timing spec (defined as > 10ms) */
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mdelay(10);
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/* board_dp_backlight_pwm */
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gpio_direction_output(EXYNOS5_GPIO_B20, 1);
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/* T6 in the LCD timing spec (defined as > 10ms) */
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mdelay(10);
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/* try to set the backlight in the bridge registers */
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ret = board_dp_set_backlight(80);
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/* if we have no bridge or it does not support backlight, use a GPIO */
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if (ret == -ENODEV || ret == -ENOSYS) {
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gpio_request(EXYNOS5_GPIO_X30, "board_dp_backlight_en");
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gpio_direction_output(EXYNOS5_GPIO_X30, 1);
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}
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}
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void exynos_lcd_power_on(void)
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{
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struct udevice *dev;
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int ret;
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debug("%s\n", __func__);
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ret = regulator_get_by_platname("lcd_vdd", &dev);
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if (!ret)
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ret = regulator_set_enable(dev, true);
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if (ret)
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debug("Failed to enable LCD panel: ret=%d\n", ret);
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ret = board_dp_bridge_setup(gd->fdt_blob);
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if (ret && ret != -ENODEV)
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printf("LCD bridge failed to enable: %d\n", ret);
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}
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#endif
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#ifdef CONFIG_USB_DWC3
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static struct dwc3_device dwc3_device_data = {
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.maximum_speed = USB_SPEED_SUPER,
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.base = 0x12400000,
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.dr_mode = USB_DR_MODE_PERIPHERAL,
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.index = 0,
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};
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int usb_gadget_handle_interrupts(void)
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{
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dwc3_uboot_handle_interrupt(0);
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return 0;
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}
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int board_usb_init(int index, enum usb_init_type init)
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{
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struct exynos_usb3_phy *phy = (struct exynos_usb3_phy *)
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samsung_get_base_usb3_phy();
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if (!phy) {
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error("usb3 phy not supported");
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return -ENODEV;
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}
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set_usbdrd_phy_ctrl(POWER_USB_DRD_PHY_CTRL_EN);
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exynos5_usb3_phy_init(phy);
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return dwc3_uboot_init(&dwc3_device_data);
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}
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#endif
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#ifdef CONFIG_SET_DFU_ALT_INFO
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char *get_dfu_alt_system(char *interface, char *devstr)
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{
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char *info = "Not supported!";
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if (board_is_odroidxu4())
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return info;
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return getenv("dfu_alt_system");
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}
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char *get_dfu_alt_boot(char *interface, char *devstr)
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{
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char *info = "Not supported!";
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struct mmc *mmc;
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char *alt_boot;
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int dev_num;
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if (board_is_odroidxu4())
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return info;
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dev_num = simple_strtoul(devstr, NULL, 10);
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mmc = find_mmc_device(dev_num);
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if (!mmc)
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return NULL;
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if (mmc_init(mmc))
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return NULL;
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if (IS_SD(mmc))
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alt_boot = CONFIG_DFU_ALT_BOOT_SD;
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else
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alt_boot = CONFIG_DFU_ALT_BOOT_EMMC;
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return alt_boot;
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}
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#endif
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