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https://github.com/brain-hackers/u-boot-brain
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![Heiko Schocher](/assets/img/avatar_default.png)
resync ubi subsystem with linux: commit 455c6fdbd219161bd09b1165f11699d6d73de11c Author: Linus Torvalds <torvalds@linux-foundation.org> Date: Sun Mar 30 20:40:15 2014 -0700 Linux 3.14 A nice side effect of this, is we introduce UBI Fastmap support to U-Boot. Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Tom Rini <trini@ti.com> Cc: Marek Vasut <marex@denx.de> Cc: Sergey Lapin <slapin@ossfans.org> Cc: Scott Wood <scottwood@freescale.com> Cc: Joerg Krause <jkrause@posteo.de>
570 lines
13 KiB
C
570 lines
13 KiB
C
/*
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* S5PC100 OneNAND driver at U-Boot
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*
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* Copyright (C) 2008-2009 Samsung Electronics
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* Kyungmin Park <kyungmin.park@samsung.com>
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*
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* Implementation:
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* Emulate the pseudo BufferRAM
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <malloc.h>
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#include <linux/compat.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/onenand.h>
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#include <linux/mtd/flashchip.h>
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#include <linux/mtd/samsung_onenand.h>
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#include <asm/io.h>
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#include <asm/errno.h>
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#define ONENAND_ERASE_STATUS 0x00
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#define ONENAND_MULTI_ERASE_SET 0x01
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#define ONENAND_ERASE_START 0x03
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#define ONENAND_UNLOCK_START 0x08
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#define ONENAND_UNLOCK_END 0x09
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#define ONENAND_LOCK_START 0x0A
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#define ONENAND_LOCK_END 0x0B
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#define ONENAND_LOCK_TIGHT_START 0x0C
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#define ONENAND_LOCK_TIGHT_END 0x0D
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#define ONENAND_UNLOCK_ALL 0x0E
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#define ONENAND_OTP_ACCESS 0x12
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#define ONENAND_SPARE_ACCESS_ONLY 0x13
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#define ONENAND_MAIN_ACCESS_ONLY 0x14
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#define ONENAND_ERASE_VERIFY 0x15
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#define ONENAND_MAIN_SPARE_ACCESS 0x16
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#define ONENAND_PIPELINE_READ 0x4000
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#if defined(CONFIG_S5P)
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#define MAP_00 (0x0 << 26)
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#define MAP_01 (0x1 << 26)
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#define MAP_10 (0x2 << 26)
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#define MAP_11 (0x3 << 26)
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#endif
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/* read/write of XIP buffer */
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#define CMD_MAP_00(mem_addr) (MAP_00 | ((mem_addr) << 1))
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/* read/write to the memory device */
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#define CMD_MAP_01(mem_addr) (MAP_01 | (mem_addr))
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/* control special functions of the memory device */
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#define CMD_MAP_10(mem_addr) (MAP_10 | (mem_addr))
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/* direct interface(direct access) with the memory device */
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#define CMD_MAP_11(mem_addr) (MAP_11 | ((mem_addr) << 2))
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struct s3c_onenand {
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struct mtd_info *mtd;
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void __iomem *base;
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void __iomem *ahb_addr;
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int bootram_command;
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void __iomem *page_buf;
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void __iomem *oob_buf;
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unsigned int (*mem_addr)(int fba, int fpa, int fsa);
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struct samsung_onenand *reg;
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};
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static struct s3c_onenand *onenand;
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static int s3c_read_cmd(unsigned int cmd)
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{
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return readl(onenand->ahb_addr + cmd);
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}
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static void s3c_write_cmd(int value, unsigned int cmd)
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{
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writel(value, onenand->ahb_addr + cmd);
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}
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/*
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* MEM_ADDR
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*
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* fba: flash block address
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* fpa: flash page address
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* fsa: flash sector address
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*
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* return the buffer address on the memory device
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* It will be combined with CMD_MAP_XX
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*/
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#if defined(CONFIG_S5P)
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static unsigned int s3c_mem_addr(int fba, int fpa, int fsa)
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{
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return (fba << 13) | (fpa << 7) | (fsa << 5);
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}
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#endif
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static void s3c_onenand_reset(void)
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{
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unsigned long timeout = 0x10000;
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int stat;
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writel(ONENAND_MEM_RESET_COLD, &onenand->reg->mem_reset);
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while (timeout--) {
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stat = readl(&onenand->reg->int_err_stat);
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if (stat & RST_CMP)
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break;
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}
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stat = readl(&onenand->reg->int_err_stat);
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writel(stat, &onenand->reg->int_err_ack);
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/* Clear interrupt */
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writel(0x0, &onenand->reg->int_err_ack);
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/* Clear the ECC status */
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writel(0x0, &onenand->reg->ecc_err_stat);
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}
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static unsigned short s3c_onenand_readw(void __iomem *addr)
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{
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struct onenand_chip *this = onenand->mtd->priv;
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int reg = addr - this->base;
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int word_addr = reg >> 1;
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int value;
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/* It's used for probing time */
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switch (reg) {
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case ONENAND_REG_MANUFACTURER_ID:
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return readl(&onenand->reg->manufact_id);
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case ONENAND_REG_DEVICE_ID:
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return readl(&onenand->reg->device_id);
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case ONENAND_REG_VERSION_ID:
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return readl(&onenand->reg->flash_ver_id);
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case ONENAND_REG_DATA_BUFFER_SIZE:
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return readl(&onenand->reg->data_buf_size);
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case ONENAND_REG_TECHNOLOGY:
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return readl(&onenand->reg->tech);
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case ONENAND_REG_SYS_CFG1:
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return readl(&onenand->reg->mem_cfg);
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/* Used at unlock all status */
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case ONENAND_REG_CTRL_STATUS:
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return 0;
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case ONENAND_REG_WP_STATUS:
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return ONENAND_WP_US;
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default:
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break;
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}
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/* BootRAM access control */
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if (reg < ONENAND_DATARAM && onenand->bootram_command) {
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if (word_addr == 0)
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return readl(&onenand->reg->manufact_id);
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if (word_addr == 1)
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return readl(&onenand->reg->device_id);
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if (word_addr == 2)
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return readl(&onenand->reg->flash_ver_id);
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}
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value = s3c_read_cmd(CMD_MAP_11(word_addr)) & 0xffff;
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printk(KERN_INFO "s3c_onenand_readw: Illegal access"
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" at reg 0x%x, value 0x%x\n", word_addr, value);
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return value;
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}
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static void s3c_onenand_writew(unsigned short value, void __iomem *addr)
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{
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struct onenand_chip *this = onenand->mtd->priv;
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int reg = addr - this->base;
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int word_addr = reg >> 1;
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/* It's used for probing time */
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switch (reg) {
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case ONENAND_REG_SYS_CFG1:
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writel(value, &onenand->reg->mem_cfg);
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return;
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case ONENAND_REG_START_ADDRESS1:
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case ONENAND_REG_START_ADDRESS2:
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return;
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/* Lock/lock-tight/unlock/unlock_all */
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case ONENAND_REG_START_BLOCK_ADDRESS:
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return;
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default:
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break;
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}
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/* BootRAM access control */
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if (reg < ONENAND_DATARAM) {
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if (value == ONENAND_CMD_READID) {
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onenand->bootram_command = 1;
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return;
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}
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if (value == ONENAND_CMD_RESET) {
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writel(ONENAND_MEM_RESET_COLD,
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&onenand->reg->mem_reset);
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onenand->bootram_command = 0;
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return;
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}
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}
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printk(KERN_INFO "s3c_onenand_writew: Illegal access"
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" at reg 0x%x, value 0x%x\n", word_addr, value);
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s3c_write_cmd(value, CMD_MAP_11(word_addr));
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}
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static int s3c_onenand_wait(struct mtd_info *mtd, int state)
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{
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unsigned int flags = INT_ACT;
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unsigned int stat, ecc;
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unsigned long timeout = 0x100000;
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switch (state) {
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case FL_READING:
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flags |= BLK_RW_CMP | LOAD_CMP;
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break;
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case FL_WRITING:
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flags |= BLK_RW_CMP | PGM_CMP;
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break;
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case FL_ERASING:
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flags |= BLK_RW_CMP | ERS_CMP;
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break;
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case FL_LOCKING:
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flags |= BLK_RW_CMP;
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break;
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default:
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break;
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}
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while (timeout--) {
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stat = readl(&onenand->reg->int_err_stat);
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if (stat & flags)
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break;
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}
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/* To get correct interrupt status in timeout case */
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stat = readl(&onenand->reg->int_err_stat);
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writel(stat, &onenand->reg->int_err_ack);
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/*
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* In the Spec. it checks the controller status first
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* However if you get the correct information in case of
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* power off recovery (POR) test, it should read ECC status first
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*/
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if (stat & LOAD_CMP) {
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ecc = readl(&onenand->reg->ecc_err_stat);
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if (ecc & ONENAND_ECC_4BIT_UNCORRECTABLE) {
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printk(KERN_INFO "%s: ECC error = 0x%04x\n",
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__func__, ecc);
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mtd->ecc_stats.failed++;
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return -EBADMSG;
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}
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}
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if (stat & (LOCKED_BLK | ERS_FAIL | PGM_FAIL | LD_FAIL_ECC_ERR)) {
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printk(KERN_INFO "%s: controller error = 0x%04x\n",
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__func__, stat);
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if (stat & LOCKED_BLK)
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printk(KERN_INFO "%s: it's locked error = 0x%04x\n",
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__func__, stat);
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return -EIO;
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}
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return 0;
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}
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static int s3c_onenand_command(struct mtd_info *mtd, int cmd,
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loff_t addr, size_t len)
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{
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struct onenand_chip *this = mtd->priv;
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unsigned int *m, *s;
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int fba, fpa, fsa = 0;
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unsigned int mem_addr;
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int i, mcount, scount;
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int index;
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fba = (int) (addr >> this->erase_shift);
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fpa = (int) (addr >> this->page_shift);
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fpa &= this->page_mask;
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mem_addr = onenand->mem_addr(fba, fpa, fsa);
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switch (cmd) {
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case ONENAND_CMD_READ:
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case ONENAND_CMD_READOOB:
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case ONENAND_CMD_BUFFERRAM:
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ONENAND_SET_NEXT_BUFFERRAM(this);
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default:
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break;
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}
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index = ONENAND_CURRENT_BUFFERRAM(this);
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/*
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* Emulate Two BufferRAMs and access with 4 bytes pointer
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*/
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m = (unsigned int *) onenand->page_buf;
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s = (unsigned int *) onenand->oob_buf;
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if (index) {
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m += (this->writesize >> 2);
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s += (mtd->oobsize >> 2);
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}
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mcount = mtd->writesize >> 2;
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scount = mtd->oobsize >> 2;
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switch (cmd) {
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case ONENAND_CMD_READ:
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/* Main */
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for (i = 0; i < mcount; i++)
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*m++ = s3c_read_cmd(CMD_MAP_01(mem_addr));
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return 0;
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case ONENAND_CMD_READOOB:
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writel(TSRF, &onenand->reg->trans_spare);
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/* Main */
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for (i = 0; i < mcount; i++)
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*m++ = s3c_read_cmd(CMD_MAP_01(mem_addr));
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/* Spare */
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for (i = 0; i < scount; i++)
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*s++ = s3c_read_cmd(CMD_MAP_01(mem_addr));
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writel(0, &onenand->reg->trans_spare);
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return 0;
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case ONENAND_CMD_PROG:
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/* Main */
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for (i = 0; i < mcount; i++)
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s3c_write_cmd(*m++, CMD_MAP_01(mem_addr));
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return 0;
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case ONENAND_CMD_PROGOOB:
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writel(TSRF, &onenand->reg->trans_spare);
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/* Main - dummy write */
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for (i = 0; i < mcount; i++)
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s3c_write_cmd(0xffffffff, CMD_MAP_01(mem_addr));
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/* Spare */
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for (i = 0; i < scount; i++)
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s3c_write_cmd(*s++, CMD_MAP_01(mem_addr));
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writel(0, &onenand->reg->trans_spare);
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return 0;
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case ONENAND_CMD_UNLOCK_ALL:
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s3c_write_cmd(ONENAND_UNLOCK_ALL, CMD_MAP_10(mem_addr));
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return 0;
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case ONENAND_CMD_ERASE:
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s3c_write_cmd(ONENAND_ERASE_START, CMD_MAP_10(mem_addr));
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return 0;
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case ONENAND_CMD_MULTIBLOCK_ERASE:
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s3c_write_cmd(ONENAND_MULTI_ERASE_SET, CMD_MAP_10(mem_addr));
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return 0;
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case ONENAND_CMD_ERASE_VERIFY:
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s3c_write_cmd(ONENAND_ERASE_VERIFY, CMD_MAP_10(mem_addr));
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return 0;
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default:
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break;
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}
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return 0;
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}
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static unsigned char *s3c_get_bufferram(struct mtd_info *mtd, int area)
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{
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struct onenand_chip *this = mtd->priv;
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int index = ONENAND_CURRENT_BUFFERRAM(this);
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unsigned char *p;
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if (area == ONENAND_DATARAM) {
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p = (unsigned char *) onenand->page_buf;
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if (index == 1)
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p += this->writesize;
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} else {
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p = (unsigned char *) onenand->oob_buf;
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if (index == 1)
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p += mtd->oobsize;
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}
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return p;
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}
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static int onenand_read_bufferram(struct mtd_info *mtd, loff_t addr, int area,
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unsigned char *buffer, int offset,
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size_t count)
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{
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unsigned char *p;
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p = s3c_get_bufferram(mtd, area);
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memcpy(buffer, p + offset, count);
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return 0;
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}
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static int onenand_write_bufferram(struct mtd_info *mtd, loff_t addr, int area,
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const unsigned char *buffer, int offset,
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size_t count)
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{
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unsigned char *p;
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p = s3c_get_bufferram(mtd, area);
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memcpy(p + offset, buffer, count);
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return 0;
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}
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static int s3c_onenand_bbt_wait(struct mtd_info *mtd, int state)
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{
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struct samsung_onenand *reg = (struct samsung_onenand *)onenand->base;
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unsigned int flags = INT_ACT | LOAD_CMP;
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unsigned int stat;
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unsigned long timeout = 0x10000;
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while (timeout--) {
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stat = readl(®->int_err_stat);
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if (stat & flags)
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break;
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}
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/* To get correct interrupt status in timeout case */
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stat = readl(&onenand->reg->int_err_stat);
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writel(stat, &onenand->reg->int_err_ack);
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if (stat & LD_FAIL_ECC_ERR) {
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s3c_onenand_reset();
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return ONENAND_BBT_READ_ERROR;
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}
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if (stat & LOAD_CMP) {
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int ecc = readl(&onenand->reg->ecc_err_stat);
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if (ecc & ONENAND_ECC_4BIT_UNCORRECTABLE) {
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s3c_onenand_reset();
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return ONENAND_BBT_READ_ERROR;
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}
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}
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return 0;
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}
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static void s3c_onenand_check_lock_status(struct mtd_info *mtd)
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{
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struct onenand_chip *this = mtd->priv;
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unsigned int block, end;
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end = this->chipsize >> this->erase_shift;
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for (block = 0; block < end; block++) {
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s3c_read_cmd(CMD_MAP_01(onenand->mem_addr(block, 0, 0)));
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if (readl(&onenand->reg->int_err_stat) & LOCKED_BLK) {
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printf("block %d is write-protected!\n", block);
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writel(LOCKED_BLK, &onenand->reg->int_err_ack);
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}
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}
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}
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static void s3c_onenand_do_lock_cmd(struct mtd_info *mtd, loff_t ofs,
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size_t len, int cmd)
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{
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struct onenand_chip *this = mtd->priv;
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int start, end, start_mem_addr, end_mem_addr;
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start = ofs >> this->erase_shift;
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start_mem_addr = onenand->mem_addr(start, 0, 0);
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end = start + (len >> this->erase_shift) - 1;
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end_mem_addr = onenand->mem_addr(end, 0, 0);
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if (cmd == ONENAND_CMD_LOCK) {
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s3c_write_cmd(ONENAND_LOCK_START, CMD_MAP_10(start_mem_addr));
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s3c_write_cmd(ONENAND_LOCK_END, CMD_MAP_10(end_mem_addr));
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} else {
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s3c_write_cmd(ONENAND_UNLOCK_START, CMD_MAP_10(start_mem_addr));
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s3c_write_cmd(ONENAND_UNLOCK_END, CMD_MAP_10(end_mem_addr));
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}
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this->wait(mtd, FL_LOCKING);
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}
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static void s3c_onenand_unlock_all(struct mtd_info *mtd)
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{
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struct onenand_chip *this = mtd->priv;
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loff_t ofs = 0;
|
|
size_t len = this->chipsize;
|
|
|
|
/* FIXME workaround */
|
|
this->subpagesize = mtd->writesize;
|
|
mtd->subpage_sft = 0;
|
|
|
|
if (this->options & ONENAND_HAS_UNLOCK_ALL) {
|
|
/* Write unlock command */
|
|
this->command(mtd, ONENAND_CMD_UNLOCK_ALL, 0, 0);
|
|
|
|
/* No need to check return value */
|
|
this->wait(mtd, FL_LOCKING);
|
|
|
|
/* Workaround for all block unlock in DDP */
|
|
if (!ONENAND_IS_DDP(this)) {
|
|
s3c_onenand_check_lock_status(mtd);
|
|
return;
|
|
}
|
|
|
|
/* All blocks on another chip */
|
|
ofs = this->chipsize >> 1;
|
|
len = this->chipsize >> 1;
|
|
}
|
|
|
|
s3c_onenand_do_lock_cmd(mtd, ofs, len, ONENAND_CMD_UNLOCK);
|
|
s3c_onenand_check_lock_status(mtd);
|
|
}
|
|
|
|
int s5pc110_chip_probe(struct mtd_info *mtd)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
int s5pc210_chip_probe(struct mtd_info *mtd)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
void s3c_onenand_init(struct mtd_info *mtd)
|
|
{
|
|
struct onenand_chip *this = mtd->priv;
|
|
u32 size = (4 << 10); /* 4 KiB */
|
|
|
|
onenand = malloc(sizeof(struct s3c_onenand));
|
|
if (!onenand)
|
|
return;
|
|
|
|
onenand->page_buf = malloc(size * sizeof(char));
|
|
if (!onenand->page_buf)
|
|
return;
|
|
memset(onenand->page_buf, 0xff, size);
|
|
|
|
onenand->oob_buf = malloc(128 * sizeof(char));
|
|
if (!onenand->oob_buf)
|
|
return;
|
|
memset(onenand->oob_buf, 0xff, 128);
|
|
|
|
onenand->mtd = mtd;
|
|
|
|
#if defined(CONFIG_S5P)
|
|
onenand->base = (void *)0xE7100000;
|
|
onenand->ahb_addr = (void *)0xB0000000;
|
|
#endif
|
|
onenand->mem_addr = s3c_mem_addr;
|
|
onenand->reg = (struct samsung_onenand *)onenand->base;
|
|
|
|
this->read_word = s3c_onenand_readw;
|
|
this->write_word = s3c_onenand_writew;
|
|
|
|
this->wait = s3c_onenand_wait;
|
|
this->bbt_wait = s3c_onenand_bbt_wait;
|
|
this->unlock_all = s3c_onenand_unlock_all;
|
|
this->command = s3c_onenand_command;
|
|
|
|
this->read_bufferram = onenand_read_bufferram;
|
|
this->write_bufferram = onenand_write_bufferram;
|
|
|
|
this->options |= ONENAND_RUNTIME_BADBLOCK_CHECK;
|
|
}
|