mirror of
https://github.com/brain-hackers/u-boot-brain
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45dee2e620
This patch fixes the re-calculation of the automatic chip select configuration for boards with two populated FLASH banks. Signed-off-by: Martin Krause <martin.krause@tqs.de>
434 lines
13 KiB
C
434 lines
13 KiB
C
/*
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* (C) Copyright 2005
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* Copyright 2004 Freescale Semiconductor.
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* (C) Copyright 2002,2003, Motorola Inc.
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* Xianghua Xiao, (X.Xiao@motorola.com)
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*
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* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <pci.h>
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#include <asm/processor.h>
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#include <asm/immap_85xx.h>
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#include <ioports.h>
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#include <flash.h>
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DECLARE_GLOBAL_DATA_PTR;
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extern flash_info_t flash_info[]; /* FLASH chips info */
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void local_bus_init (void);
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ulong flash_get_size (ulong base, int banknum);
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#ifdef CONFIG_PS2MULT
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void ps2mult_early_init (void);
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#endif
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#ifdef CONFIG_CPM2
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/*
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* I/O Port configuration table
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*
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* if conf is 1, then that port pin will be configured at boot time
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* according to the five values podr/pdir/ppar/psor/pdat for that entry
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*/
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const iop_conf_t iop_conf_tab[4][32] = {
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/* Port A: conf, ppar, psor, pdir, podr, pdat */
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{
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{1, 1, 1, 0, 0, 0}, /* PA31: FCC1 MII COL */
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{1, 1, 1, 0, 0, 0}, /* PA30: FCC1 MII CRS */
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{1, 1, 1, 1, 0, 0}, /* PA29: FCC1 MII TX_ER */
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{1, 1, 1, 1, 0, 0}, /* PA28: FCC1 MII TX_EN */
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{1, 1, 1, 0, 0, 0}, /* PA27: FCC1 MII RX_DV */
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{1, 1, 1, 0, 0, 0}, /* PA26: FCC1 MII RX_ER */
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{0, 1, 0, 1, 0, 0}, /* PA25: FCC1 ATMTXD[0] */
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{0, 1, 0, 1, 0, 0}, /* PA24: FCC1 ATMTXD[1] */
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{0, 1, 0, 1, 0, 0}, /* PA23: FCC1 ATMTXD[2] */
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{0, 1, 0, 1, 0, 0}, /* PA22: FCC1 ATMTXD[3] */
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{1, 1, 0, 1, 0, 0}, /* PA21: FCC1 MII TxD[3] */
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{1, 1, 0, 1, 0, 0}, /* PA20: FCC1 MII TxD[2] */
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{1, 1, 0, 1, 0, 0}, /* PA19: FCC1 MII TxD[1] */
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{1, 1, 0, 1, 0, 0}, /* PA18: FCC1 MII TxD[0] */
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{1, 1, 0, 0, 0, 0}, /* PA17: FCC1 MII RxD[0] */
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{1, 1, 0, 0, 0, 0}, /* PA16: FCC1 MII RxD[1] */
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{1, 1, 0, 0, 0, 0}, /* PA15: FCC1 MII RxD[2] */
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{1, 1, 0, 0, 0, 0}, /* PA14: FCC1 MII RxD[3] */
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{0, 1, 0, 0, 0, 0}, /* PA13: FCC1 ATMRXD[3] */
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{0, 1, 0, 0, 0, 0}, /* PA12: FCC1 ATMRXD[2] */
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{0, 1, 0, 0, 0, 0}, /* PA11: FCC1 ATMRXD[1] */
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{0, 1, 0, 0, 0, 0}, /* PA10: FCC1 ATMRXD[0] */
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{0, 1, 1, 1, 0, 0}, /* PA9 : FCC1 L1TXD */
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{0, 1, 1, 0, 0, 0}, /* PA8 : FCC1 L1RXD */
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{0, 0, 0, 1, 0, 0}, /* PA7 : PA7 */
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{0, 1, 1, 1, 0, 0}, /* PA6 : TDM A1 L1RSYNC */
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{0, 0, 0, 1, 0, 0}, /* PA5 : PA5 */
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{0, 0, 0, 1, 0, 0}, /* PA4 : PA4 */
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{0, 0, 0, 1, 0, 0}, /* PA3 : PA3 */
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{0, 0, 0, 1, 0, 0}, /* PA2 : PA2 */
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{0, 0, 0, 0, 0, 0}, /* PA1 : FREERUN */
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{0, 0, 0, 1, 0, 0} /* PA0 : PA0 */
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},
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/* Port B: conf, ppar, psor, pdir, podr, pdat */
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{
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{1, 1, 0, 1, 0, 0}, /* PB31: FCC2 MII TX_ER */
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{1, 1, 0, 0, 0, 0}, /* PB30: FCC2 MII RX_DV */
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{1, 1, 1, 1, 0, 0}, /* PB29: FCC2 MII TX_EN */
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{1, 1, 0, 0, 0, 0}, /* PB28: FCC2 MII RX_ER */
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{1, 1, 0, 0, 0, 0}, /* PB27: FCC2 MII COL */
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{1, 1, 0, 0, 0, 0}, /* PB26: FCC2 MII CRS */
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{1, 1, 0, 1, 0, 0}, /* PB25: FCC2 MII TxD[3] */
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{1, 1, 0, 1, 0, 0}, /* PB24: FCC2 MII TxD[2] */
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{1, 1, 0, 1, 0, 0}, /* PB23: FCC2 MII TxD[1] */
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{1, 1, 0, 1, 0, 0}, /* PB22: FCC2 MII TxD[0] */
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{1, 1, 0, 0, 0, 0}, /* PB21: FCC2 MII RxD[0] */
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{1, 1, 0, 0, 0, 0}, /* PB20: FCC2 MII RxD[1] */
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{1, 1, 0, 0, 0, 0}, /* PB19: FCC2 MII RxD[2] */
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{1, 1, 0, 0, 0, 0}, /* PB18: FCC2 MII RxD[3] */
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{1, 1, 0, 0, 0, 0}, /* PB17: FCC3:RX_DIV */
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{1, 1, 0, 0, 0, 0}, /* PB16: FCC3:RX_ERR */
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{1, 1, 0, 1, 0, 0}, /* PB15: FCC3:TX_ERR */
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{1, 1, 0, 1, 0, 0}, /* PB14: FCC3:TX_EN */
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{1, 1, 0, 0, 0, 0}, /* PB13: FCC3:COL */
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{1, 1, 0, 0, 0, 0}, /* PB12: FCC3:CRS */
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{1, 1, 0, 0, 0, 0}, /* PB11: FCC3:RXD */
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{1, 1, 0, 0, 0, 0}, /* PB10: FCC3:RXD */
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{1, 1, 0, 0, 0, 0}, /* PB9 : FCC3:RXD */
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{1, 1, 0, 0, 0, 0}, /* PB8 : FCC3:RXD */
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{1, 1, 0, 1, 0, 0}, /* PB7 : FCC3:TXD */
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{1, 1, 0, 1, 0, 0}, /* PB6 : FCC3:TXD */
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{1, 1, 0, 1, 0, 0}, /* PB5 : FCC3:TXD */
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{1, 1, 0, 1, 0, 0}, /* PB4 : FCC3:TXD */
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{0, 0, 0, 0, 0, 0}, /* PB3 : pin doesn't exist */
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{0, 0, 0, 0, 0, 0}, /* PB2 : pin doesn't exist */
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{0, 0, 0, 0, 0, 0}, /* PB1 : pin doesn't exist */
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{0, 0, 0, 0, 0, 0} /* PB0 : pin doesn't exist */
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},
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/* Port C: conf, ppar, psor, pdir, podr, pdat */
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{
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{0, 0, 0, 1, 0, 0}, /* PC31: PC31 */
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{0, 0, 0, 1, 0, 0}, /* PC30: PC30 */
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{0, 1, 1, 0, 0, 0}, /* PC29: SCC1 EN *CLSN */
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{0, 0, 0, 1, 0, 0}, /* PC28: PC28 */
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{0, 0, 0, 1, 0, 0}, /* PC27: UART Clock in */
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{0, 0, 0, 1, 0, 0}, /* PC26: PC26 */
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{0, 0, 0, 1, 0, 0}, /* PC25: PC25 */
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{0, 0, 0, 1, 0, 0}, /* PC24: PC24 */
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{0, 1, 0, 1, 0, 0}, /* PC23: ATMTFCLK */
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{0, 1, 0, 0, 0, 0}, /* PC22: ATMRFCLK */
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{1, 1, 0, 0, 0, 0}, /* PC21: SCC1 EN RXCLK */
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{1, 1, 0, 0, 0, 0}, /* PC20: SCC1 EN TXCLK */
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{1, 1, 0, 0, 0, 0}, /* PC19: FCC2 MII RX_CLK CLK13 */
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{1, 1, 0, 0, 0, 0}, /* PC18: FCC Tx Clock (CLK14) */
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{1, 1, 0, 0, 0, 0}, /* PC17: PC17 */
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{1, 1, 0, 0, 0, 0}, /* PC16: FCC Tx Clock (CLK16) */
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{0, 1, 0, 0, 0, 0}, /* PC15: PC15 */
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{0, 1, 0, 0, 0, 0}, /* PC14: SCC1 EN *CD */
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{0, 1, 0, 0, 0, 0}, /* PC13: PC13 */
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{0, 1, 0, 1, 0, 0}, /* PC12: PC12 */
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{0, 0, 0, 1, 0, 0}, /* PC11: LXT971 transmit control */
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{0, 0, 0, 1, 0, 0}, /* PC10: FETHMDC */
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{0, 0, 0, 0, 0, 0}, /* PC9 : FETHMDIO */
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{0, 0, 0, 1, 0, 0}, /* PC8 : PC8 */
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{0, 0, 0, 1, 0, 0}, /* PC7 : PC7 */
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{0, 0, 0, 1, 0, 0}, /* PC6 : PC6 */
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{0, 0, 0, 1, 0, 0}, /* PC5 : PC5 */
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{0, 0, 0, 1, 0, 0}, /* PC4 : PC4 */
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{0, 0, 0, 1, 0, 0}, /* PC3 : PC3 */
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{0, 0, 0, 1, 0, 1}, /* PC2 : ENET FDE */
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{0, 0, 0, 1, 0, 0}, /* PC1 : ENET DSQE */
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{0, 0, 0, 1, 0, 0}, /* PC0 : ENET LBK */
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},
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/* Port D: conf, ppar, psor, pdir, podr, pdat */
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{
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#ifdef CONFIG_TQM8560
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{1, 1, 0, 0, 0, 0}, /* PD31: SCC1 EN RxD */
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{1, 1, 1, 1, 0, 0}, /* PD30: SCC1 EN TxD */
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{1, 1, 0, 1, 0, 0}, /* PD29: SCC1 EN TENA */
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#else /* !CONFIG_TQM8560 */
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{0, 0, 0, 0, 0, 0}, /* PD31: PD31 */
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{0, 0, 0, 0, 0, 0}, /* PD30: PD30 */
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{0, 0, 0, 0, 0, 0}, /* PD29: PD29 */
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#endif /* CONFIG_TQM8560 */
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{1, 1, 0, 0, 0, 0}, /* PD28: PD28 */
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{1, 1, 0, 1, 0, 0}, /* PD27: PD27 */
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{1, 1, 0, 1, 0, 0}, /* PD26: PD26 */
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{0, 0, 0, 1, 0, 0}, /* PD25: PD25 */
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{0, 0, 0, 1, 0, 0}, /* PD24: PD24 */
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{0, 0, 0, 1, 0, 0}, /* PD23: PD23 */
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{0, 0, 0, 1, 0, 0}, /* PD22: PD22 */
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{0, 0, 0, 1, 0, 0}, /* PD21: PD21 */
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{0, 0, 0, 1, 0, 0}, /* PD20: PD20 */
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{0, 0, 0, 1, 0, 0}, /* PD19: PD19 */
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{0, 0, 0, 1, 0, 0}, /* PD18: PD18 */
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{0, 1, 0, 0, 0, 0}, /* PD17: FCC1 ATMRXPRTY */
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{0, 1, 0, 1, 0, 0}, /* PD16: FCC1 ATMTXPRTY */
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{0, 1, 1, 0, 1, 0}, /* PD15: I2C SDA */
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{0, 0, 0, 1, 0, 0}, /* PD14: LED */
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{0, 0, 0, 0, 0, 0}, /* PD13: PD13 */
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{0, 0, 0, 0, 0, 0}, /* PD12: PD12 */
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{0, 0, 0, 0, 0, 0}, /* PD11: PD11 */
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{0, 0, 0, 0, 0, 0}, /* PD10: PD10 */
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{0, 1, 0, 1, 0, 0}, /* PD9 : SMC1 TXD */
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{0, 1, 0, 0, 0, 0}, /* PD8 : SMC1 RXD */
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{0, 0, 0, 1, 0, 1}, /* PD7 : PD7 */
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{0, 0, 0, 1, 0, 1}, /* PD6 : PD6 */
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{0, 0, 0, 1, 0, 1}, /* PD5 : PD5 */
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{0, 0, 0, 1, 0, 1}, /* PD4 : PD4 */
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{0, 0, 0, 0, 0, 0}, /* PD3 : pin doesn't exist */
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{0, 0, 0, 0, 0, 0}, /* PD2 : pin doesn't exist */
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{0, 0, 0, 0, 0, 0}, /* PD1 : pin doesn't exist */
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{0, 0, 0, 0, 0, 0} /* PD0 : pin doesn't exist */
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}
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};
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#endif /* CONFIG_CPM2 */
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#define CASL_STRING1 "casl=xx"
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#define CASL_STRING2 "casl="
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static const int casl_table[] = { 20, 25, 30 };
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#define N_CASL (sizeof(casl_table) / sizeof(casl_table[0]))
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int cas_latency (void)
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{
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char *s = getenv ("serial#");
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int casl;
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int val;
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int i;
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casl = CONFIG_DDR_DEFAULT_CL;
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if (s != NULL) {
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if (strncmp(s + strlen (s) - strlen (CASL_STRING1),
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CASL_STRING2, strlen (CASL_STRING2)) == 0) {
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val = simple_strtoul (s + strlen (s) - 2, NULL, 10);
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for (i = 0; i < N_CASL; ++i) {
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if (val == casl_table[i]) {
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return val;
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}
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}
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}
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}
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return casl;
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}
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int checkboard (void)
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{
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char *s = getenv ("serial#");
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printf ("Board: %s", CONFIG_BOARDNAME);
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if (s != NULL) {
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puts (", serial# ");
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puts (s);
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}
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putc ('\n');
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#ifdef CONFIG_PCI
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printf ("PCI1: 32 bit, %d MHz (compiled)\n",
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CONFIG_SYS_CLK_FREQ / 1000000);
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#else
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printf ("PCI1: disabled\n");
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#endif
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/*
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* Initialize local bus.
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*/
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local_bus_init ();
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return 0;
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}
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int misc_init_r (void)
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{
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volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR);
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/*
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* Adjust flash start and offset to detected values
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*/
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gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
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gd->bd->bi_flashoffset = 0;
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/*
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* Recalculate CS configuration if second FLASH bank is available
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*/
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if (flash_info[0].size > 0) {
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memctl->or1 = ((-flash_info[0].size) & 0xffff8000) |
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(CFG_OR1_PRELIM & 0x00007fff);
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memctl->br1 = gd->bd->bi_flashstart |
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(CFG_BR1_PRELIM & 0x00007fff);
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/*
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* Re-check to get correct base address for bank 1
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*/
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flash_get_size (gd->bd->bi_flashstart, 0);
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} else {
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memctl->or1 = 0;
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memctl->br1 = 0;
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}
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/*
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* If bank 1 is equipped, bank 0 is mapped after bank 1
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*/
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memctl->or0 = ((-flash_info[1].size) & 0xffff8000) |
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(CFG_OR0_PRELIM & 0x00007fff);
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memctl->br0 = (gd->bd->bi_flashstart + flash_info[0].size) |
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(CFG_BR0_PRELIM & 0x00007fff);
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/*
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* Re-check to get correct base address for bank 0
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*/
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flash_get_size (gd->bd->bi_flashstart + flash_info[0].size, 1);
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/*
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* Re-do flash protection upon new addresses
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*/
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flash_protect (FLAG_PROTECT_CLEAR,
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gd->bd->bi_flashstart, 0xffffffff,
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&flash_info[CFG_MAX_FLASH_BANKS - 1]);
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/* Monitor protection ON by default */
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flash_protect (FLAG_PROTECT_SET,
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CFG_MONITOR_BASE,
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CFG_MONITOR_BASE + monitor_flash_len - 1,
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&flash_info[CFG_MAX_FLASH_BANKS - 1]);
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/* Environment protection ON by default */
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flash_protect (FLAG_PROTECT_SET,
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CFG_ENV_ADDR,
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CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
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&flash_info[CFG_MAX_FLASH_BANKS - 1]);
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#ifdef CFG_ENV_ADDR_REDUND
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/* Redundant environment protection ON by default */
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flash_protect (FLAG_PROTECT_SET,
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CFG_ENV_ADDR_REDUND,
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CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
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&flash_info[CFG_MAX_FLASH_BANKS - 1]);
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#endif
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return 0;
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}
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/*
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* Initialize Local Bus
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*/
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void local_bus_init (void)
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{
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volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
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volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
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uint clkdiv;
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uint lbc_hz;
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sys_info_t sysinfo;
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/*
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* Errata LBC11.
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* Fix Local Bus clock glitch when DLL is enabled.
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*
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* If localbus freq is < 66Mhz, DLL bypass mode must be used.
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* If localbus freq is > 133Mhz, DLL can be safely enabled.
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* Between 66 and 133, the DLL is enabled with an override workaround.
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*/
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get_sys_info (&sysinfo);
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clkdiv = lbc->lcrr & 0x0f;
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lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
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if (lbc_hz < 66) {
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lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */
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lbc->ltedr = 0xa4c80000; /* DK: !!! */
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} else if (lbc_hz >= 133) {
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lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
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} else {
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/*
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* On REV1 boards, need to change CLKDIV before enable DLL.
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* Default CLKDIV is 8, change it to 4 temporarily.
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*/
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uint pvr = get_pvr ();
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uint temp_lbcdll = 0;
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if (pvr == PVR_85xx_REV1) {
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/* FIXME: Justify the high bit here. */
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lbc->lcrr = 0x10000004;
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}
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lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
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udelay (200);
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/*
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* Sample LBC DLL ctrl reg, upshift it to set the
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* override bits.
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*/
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temp_lbcdll = gur->lbcdllcr;
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gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
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|
asm ("sync;isync;msync");
|
|
}
|
|
}
|
|
|
|
#if defined(CONFIG_PCI)
|
|
/*
|
|
* Initialize PCI Devices, report devices found.
|
|
*/
|
|
|
|
#ifndef CONFIG_PCI_PNP
|
|
static struct pci_config_table pci_mpc85xxads_config_table[] = {
|
|
{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
|
|
PCI_IDSEL_NUMBER, PCI_ANY_ID,
|
|
pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
|
|
PCI_ENET0_MEMADDR,
|
|
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}},
|
|
{}
|
|
};
|
|
#endif
|
|
|
|
static struct pci_controller hose = {
|
|
#ifndef CONFIG_PCI_PNP
|
|
config_table:pci_mpc85xxads_config_table,
|
|
#endif
|
|
};
|
|
|
|
#endif /* CONFIG_PCI */
|
|
|
|
void pci_init_board (void)
|
|
{
|
|
#ifdef CONFIG_PCI
|
|
pci_mpc85xx_init (&hose);
|
|
#endif /* CONFIG_PCI */
|
|
}
|
|
|
|
#ifdef CONFIG_BOARD_EARLY_INIT_R
|
|
int board_early_init_r (void)
|
|
{
|
|
#ifdef CONFIG_PS2MULT
|
|
ps2mult_early_init ();
|
|
#endif /* CONFIG_PS2MULT */
|
|
return (0);
|
|
}
|
|
#endif /* CONFIG_BOARD_EARLY_INIT_R */
|