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![Wolfgang Denk](/assets/img/avatar_default.png)
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
538 lines
14 KiB
C
538 lines
14 KiB
C
/*
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Prafulla Wadaskar <prafulla@marvell.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <netdev.h>
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#include "mv88e61xx.h"
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/*
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* Uncomment either of the following line for local debug control;
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* otherwise global debug control will apply.
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*/
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/* #undef DEBUG */
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/* #define DEBUG */
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#ifdef CONFIG_MV88E61XX_MULTICHIP_ADRMODE
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/* Chip Address mode
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* The Switch support two modes of operation
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* 1. single chip mode and
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* 2. Multi-chip mode
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* Refer section 9.2 &9.3 in chip datasheet-02 for more details
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*
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* By default single chip mode is configured
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* multichip mode operation can be configured in board header
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*/
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static int mv88e61xx_busychk_multic(char *name, u32 devaddr)
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{
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u16 reg = 0;
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u32 timeout = MV88E61XX_PHY_TIMEOUT;
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/* Poll till SMIBusy bit is clear */
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do {
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miiphy_read(name, devaddr, 0x0, ®);
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if (timeout-- == 0) {
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printf("SMI busy timeout\n");
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return -1;
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}
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} while (reg & (1 << 15));
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return 0;
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}
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static void mv88e61xx_switch_write(char *name, u32 phy_adr,
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u32 reg_ofs, u16 data)
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{
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u16 mii_dev_addr;
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/* command to read PHY dev address */
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if (miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr)) {
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printf("Error..could not read PHY dev address\n");
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return;
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}
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mv88e61xx_busychk_multic(name, mii_dev_addr);
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/* Write data to Switch indirect data register */
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miiphy_write(name, mii_dev_addr, 0x1, data);
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/* Write command to Switch indirect command register (write) */
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miiphy_write(name, mii_dev_addr, 0x0,
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reg_ofs | (phy_adr << 5) | (1 << 10) | (1 << 12) | (1 <<
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15));
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}
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static void mv88e61xx_switch_read(char *name, u32 phy_adr,
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u32 reg_ofs, u16 *data)
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{
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u16 mii_dev_addr;
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/* command to read PHY dev address */
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if (miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr)) {
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printf("Error..could not read PHY dev address\n");
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return;
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}
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mv88e61xx_busychk_multic(name, mii_dev_addr);
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/* Write command to Switch indirect command register (read) */
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miiphy_write(name, mii_dev_addr, 0x0,
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reg_ofs | (phy_adr << 5) | (1 << 11) | (1 << 12) | (1 <<
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15));
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mv88e61xx_busychk_multic(name, mii_dev_addr);
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/* Read data from Switch indirect data register */
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miiphy_read(name, mii_dev_addr, 0x1, data);
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}
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#endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */
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/*
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* Convenience macros for switch device/port reads/writes
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* These macros output valid 'mv88e61xx' U_BOOT_CMDs
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*/
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#ifndef DEBUG
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#define WR_SWITCH_REG wr_switch_reg
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#define RD_SWITCH_REG rd_switch_reg
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#define WR_SWITCH_PORT_REG(n, p, r, d) \
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WR_SWITCH_REG(n, (MV88E61XX_PRT_OFST+p), r, d)
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#define RD_SWITCH_PORT_REG(n, p, r, d) \
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RD_SWITCH_REG(n, (MV88E61XX_PRT_OFST+p), r, d)
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#else
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static void WR_SWITCH_REG(char *name, u32 dev_adr, u32 reg_ofs, u16 data)
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{
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printf("mv88e61xx %s dev %02x reg %02x write %04x\n",
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name, dev_adr, reg_ofs, data);
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wr_switch_reg(name, dev_adr, reg_ofs, data);
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}
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static void RD_SWITCH_REG(char *name, u32 dev_adr, u32 reg_ofs, u16 *data)
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{
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rd_switch_reg(name, dev_adr, reg_ofs, data);
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printf("mv88e61xx %s dev %02x reg %02x read %04x\n",
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name, dev_adr, reg_ofs, *data);
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}
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static void WR_SWITCH_PORT_REG(char *name, u32 prt_adr, u32 reg_ofs,
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u16 data)
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{
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printf("mv88e61xx %s port %02x reg %02x write %04x\n",
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name, prt_adr, reg_ofs, data);
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wr_switch_reg(name, (MV88E61XX_PRT_OFST+prt_adr), reg_ofs, data);
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}
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static void RD_SWITCH_PORT_REG(char *name, u32 prt_adr, u32 reg_ofs,
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u16 *data)
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{
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rd_switch_reg(name, (MV88E61XX_PRT_OFST+prt_adr), reg_ofs, data);
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printf("mv88e61xx %s port %02x reg %02x read %04x\n",
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name, prt_adr, reg_ofs, *data);
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}
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#endif
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/*
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* Local functions to read/write registers on the switch PHYs.
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* NOTE! This goes through switch, not direct miiphy, writes and reads!
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*/
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/*
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* Make sure SMIBusy bit cleared before another
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* SMI operation can take place
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*/
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static int mv88e61xx_busychk(char *name)
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{
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u16 reg = 0;
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u32 timeout = MV88E61XX_PHY_TIMEOUT;
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do {
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rd_switch_reg(name, MV88E61XX_GLB2REG_DEVADR,
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MV88E61XX_PHY_CMD, ®);
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if (timeout-- == 0) {
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printf("SMI busy timeout\n");
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return -1;
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}
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} while (reg & 1 << 15); /* busy mask */
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return 0;
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}
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static inline int mv88e61xx_switch_miiphy_write(char *name, u32 phy,
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u32 reg, u16 data)
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{
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/* write switch data reg then cmd reg then check completion */
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wr_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA,
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data);
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wr_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_CMD,
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(MV88E61XX_PHY_WRITE_CMD | (phy << 5) | reg));
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return mv88e61xx_busychk(name);
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}
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static inline int mv88e61xx_switch_miiphy_read(char *name, u32 phy,
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u32 reg, u16 *data)
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{
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/* write switch cmd reg, check for completion */
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wr_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_CMD,
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(MV88E61XX_PHY_READ_CMD | (phy << 5) | reg));
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if (mv88e61xx_busychk(name))
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return -1;
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/* read switch data reg and return success */
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rd_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, data);
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return 0;
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}
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/*
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* Convenience macros for switch PHY reads/writes
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*/
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#ifndef DEBUG
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#define WR_SWITCH_PHY_REG mv88e61xx_switch_miiphy_write
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#define RD_SWITCH_PHY_REG mv88e61xx_switch_miiphy_read
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#else
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static inline int WR_SWITCH_PHY_REG(char *name, u32 phy_adr,
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u32 reg_ofs, u16 data)
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{
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int r = mv88e61xx_switch_miiphy_write(name, phy_adr, reg_ofs, data);
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if (r)
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printf("** ERROR writing mv88e61xx %s phy %02x reg %02x\n",
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name, phy_adr, reg_ofs);
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else
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printf("mv88e61xx %s phy %02x reg %02x write %04x\n",
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name, phy_adr, reg_ofs, data);
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return r;
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}
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static inline int RD_SWITCH_PHY_REG(char *name, u32 phy_adr,
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u32 reg_ofs, u16 *data)
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{
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int r = mv88e61xx_switch_miiphy_read(name, phy_adr, reg_ofs, data);
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if (r)
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printf("** ERROR reading mv88e61xx %s phy %02x reg %02x\n",
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name, phy_adr, reg_ofs);
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else
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printf("mv88e61xx %s phy %02x reg %02x read %04x\n",
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name, phy_adr, reg_ofs, *data);
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return r;
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}
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#endif
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static void mv88e61xx_port_vlan_config(struct mv88e61xx_config *swconfig)
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{
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u32 prt;
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u16 reg;
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char *name = swconfig->name;
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u32 port_mask = swconfig->ports_enabled;
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/* apply internal vlan config */
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for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) {
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/* only for enabled ports */
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if ((1 << prt) & port_mask) {
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/* take vlan map from swconfig */
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u8 vlanmap = swconfig->vlancfg[prt];
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/* remove disabled ports from vlan map */
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vlanmap &= swconfig->ports_enabled;
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/* apply vlan map to port */
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RD_SWITCH_PORT_REG(name, prt,
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MV88E61XX_PRT_VMAP_REG, ®);
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reg &= ~((1 << MV88E61XX_MAX_PORTS_NUM) - 1);
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reg |= vlanmap;
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WR_SWITCH_PORT_REG(name, prt,
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MV88E61XX_PRT_VMAP_REG, reg);
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}
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}
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}
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/*
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* Power up the specified port and reset PHY
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*/
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static int mv88361xx_powerup(struct mv88e61xx_config *swconfig, u32 phy)
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{
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char *name = swconfig->name;
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/* Write Copper Specific control reg1 (0x10) for-
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* Enable Phy power up
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* Energy Detect on (sense&Xmit NLP Periodically
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* reset other settings default
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*/
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if (WR_SWITCH_PHY_REG(name, phy, 0x10, 0x3360))
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return -1;
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/* Write PHY ctrl reg (0x0) to apply
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* Phy reset (set bit 15 low)
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* reset other default values
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*/
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if (WR_SWITCH_PHY_REG(name, phy, 0x00, 0x9140))
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return -1;
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return 0;
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}
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/*
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* Default Setup for LED[0]_Control (ref: Table 46 Datasheet-3)
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* is set to "On-1000Mb/s Link, Off Else"
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* This function sets it to "On-Link, Blink-Activity, Off-NoLink"
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*
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* This is optional settings may be needed on some boards
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* to setup PHY LEDs default configuration to detect 10/100/1000Mb/s
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* Link status
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*/
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static int mv88361xx_led_init(struct mv88e61xx_config *swconfig, u32 phy)
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{
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char *name = swconfig->name;
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if (swconfig->led_init != MV88E61XX_LED_INIT_EN)
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return 0;
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/* set page address to 3 */
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if (WR_SWITCH_PHY_REG(name, phy, 0x16, 0x0003))
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return -1;
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/*
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* set LED Func Ctrl reg
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* value 0x0001 = LED[0] On-Link, Blink-Activity, Off-NoLink
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*/
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if (WR_SWITCH_PHY_REG(name, phy, 0x10, 0x0001))
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return -1;
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/* set page address to 0 */
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if (WR_SWITCH_PHY_REG(name, phy, 0x16, 0x0000))
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return -1;
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return 0;
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}
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/*
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* Reverse Transmit polarity for Media Dependent Interface
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* Pins (MDIP) bits in Copper Specific Control Register 3
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* (Page 0, Reg 20 for each phy (except cpu port)
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* Reference: Section 1.1 Switch datasheet-3
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*
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* This is optional settings may be needed on some boards
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* for PHY<->magnetics h/w tuning
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*/
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static int mv88361xx_reverse_mdipn(struct mv88e61xx_config *swconfig, u32 phy)
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{
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char *name = swconfig->name;
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if (swconfig->mdip != MV88E61XX_MDIP_REVERSE)
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return 0;
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/*Reverse MDIP/N[3:0] bits */
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if (WR_SWITCH_PHY_REG(name, phy, 0x14, 0x000f))
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return -1;
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return 0;
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}
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/*
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* Marvell 88E61XX Switch initialization
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*/
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int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig)
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{
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u32 prt;
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u16 reg;
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char *idstr;
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char *name = swconfig->name;
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int time;
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if (miiphy_set_current_dev(name)) {
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printf("%s failed\n", __FUNCTION__);
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return -1;
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}
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if (!(swconfig->cpuport & ((1 << 4) | (1 << 5)))) {
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swconfig->cpuport = (1 << 5);
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printf("Invalid cpu port config, using default port5\n");
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}
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RD_SWITCH_PORT_REG(name, 0, MII_PHYSID2, ®);
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switch (reg &= 0xfff0) {
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case 0x1610:
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idstr = "88E6161";
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break;
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case 0x1650:
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idstr = "88E6165";
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break;
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case 0x1210:
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idstr = "88E6123";
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/* ports 2,3,4 not available */
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swconfig->ports_enabled &= 0x023;
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break;
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default:
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/* Could not detect switch id */
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idstr = "88E61??";
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break;
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}
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/* be sure all ports are disabled */
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for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) {
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RD_SWITCH_PORT_REG(name, prt, MV88E61XX_PRT_CTRL_REG, ®);
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reg &= ~0x3;
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WR_SWITCH_PORT_REG(name, prt, MV88E61XX_PRT_CTRL_REG, reg);
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}
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/* wait 2 ms for queues to drain */
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udelay(2000);
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/* reset switch */
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RD_SWITCH_REG(name, MV88E61XX_GLBREG_DEVADR, MV88E61XX_SGCR, ®);
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reg |= 0x8000;
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WR_SWITCH_REG(name, MV88E61XX_GLBREG_DEVADR, MV88E61XX_SGCR, reg);
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/* wait up to 1 second for switch reset complete */
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for (time = 1000; time; time--) {
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RD_SWITCH_REG(name, MV88E61XX_GLBREG_DEVADR, MV88E61XX_SGSR,
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®);
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if ((reg & 0xc800) == 0xc800)
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break;
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udelay(1000);
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}
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if (!time)
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return -1;
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/* Port based VLANs configuration */
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mv88e61xx_port_vlan_config(swconfig);
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if (swconfig->rgmii_delay == MV88E61XX_RGMII_DELAY_EN) {
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/*
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* Enable RGMII delay on Tx and Rx for CPU port
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* Ref: sec 9.5 of chip datasheet-02
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*/
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/*Force port link down */
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WR_SWITCH_PORT_REG(name, 5, MV88E61XX_PCS_CTRL_REG, 0x10);
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/* configure port RGMII delay */
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WR_SWITCH_PORT_REG(name, 4,
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MV88E61XX_RGMII_TIMECTRL_REG, 0x81e7);
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RD_SWITCH_PORT_REG(name, 5,
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MV88E61XX_RGMII_TIMECTRL_REG, ®);
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WR_SWITCH_PORT_REG(name, 5,
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MV88E61XX_RGMII_TIMECTRL_REG, reg | 0x18);
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WR_SWITCH_PORT_REG(name, 4,
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MV88E61XX_RGMII_TIMECTRL_REG, 0xc1e7);
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/* Force port to RGMII FDX 1000Base then up */
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WR_SWITCH_PORT_REG(name, 5, MV88E61XX_PCS_CTRL_REG, 0x1e);
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WR_SWITCH_PORT_REG(name, 5, MV88E61XX_PCS_CTRL_REG, 0x3e);
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}
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for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) {
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/* configure port's PHY */
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if (!((1 << prt) & swconfig->cpuport)) {
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/* port 4 has phy 6, not 4 */
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int phy = (prt == 4) ? 6 : prt;
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if (mv88361xx_powerup(swconfig, phy))
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return -1;
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if (mv88361xx_reverse_mdipn(swconfig, phy))
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return -1;
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if (mv88361xx_led_init(swconfig, phy))
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return -1;
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}
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/* set port VID to port+1 except for cpu port */
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if (!((1 << prt) & swconfig->cpuport)) {
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RD_SWITCH_PORT_REG(name, prt,
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MV88E61XX_PRT_VID_REG, ®);
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WR_SWITCH_PORT_REG(name, prt,
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MV88E61XX_PRT_VID_REG,
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(reg & ~1023) | (prt+1));
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}
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/*Program port state */
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RD_SWITCH_PORT_REG(name, prt,
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MV88E61XX_PRT_CTRL_REG, ®);
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WR_SWITCH_PORT_REG(name, prt,
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MV88E61XX_PRT_CTRL_REG,
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reg | (swconfig->portstate & 0x03));
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}
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printf("%s Initialized on %s\n", idstr, name);
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return 0;
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}
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#ifdef CONFIG_MV88E61XX_CMD
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static int
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do_switch(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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char *name, *endp;
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int write = 0;
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enum { dev, prt, phy } target = dev;
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u32 addrlo, addrhi, addr;
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u32 reglo, reghi, reg;
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u16 data, rdata;
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if (argc < 7)
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return -1;
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name = argv[1];
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if (strcmp(argv[2], "phy") == 0)
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target = phy;
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else if (strcmp(argv[2], "port") == 0)
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target = prt;
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|
else if (strcmp(argv[2], "dev") != 0)
|
|
return 1;
|
|
|
|
addrlo = simple_strtoul(argv[3], &endp, 16);
|
|
|
|
if (!*endp) {
|
|
addrhi = addrlo;
|
|
} else {
|
|
while (*endp < '0' || *endp > '9')
|
|
endp++;
|
|
addrhi = simple_strtoul(endp, NULL, 16);
|
|
}
|
|
|
|
reglo = simple_strtoul(argv[5], &endp, 16);
|
|
if (!*endp) {
|
|
reghi = reglo;
|
|
} else {
|
|
while (*endp < '0' || *endp > '9')
|
|
endp++;
|
|
reghi = simple_strtoul(endp, NULL, 16);
|
|
}
|
|
|
|
if (strcmp(argv[6], "write") == 0)
|
|
write = 1;
|
|
else if (strcmp(argv[6], "read") != 0)
|
|
return 1;
|
|
|
|
data = simple_strtoul(argv[7], NULL, 16);
|
|
|
|
for (addr = addrlo; addr <= addrhi; addr++) {
|
|
for (reg = reglo; reg <= reghi; reg++) {
|
|
if (write) {
|
|
if (target == phy)
|
|
mv88e61xx_switch_miiphy_write(
|
|
name, addr, reg, data);
|
|
else if (target == prt)
|
|
wr_switch_reg(name,
|
|
addr+MV88E61XX_PRT_OFST,
|
|
reg, data);
|
|
else
|
|
wr_switch_reg(name, addr, reg, data);
|
|
} else {
|
|
if (target == phy)
|
|
mv88e61xx_switch_miiphy_read(
|
|
name, addr, reg, &rdata);
|
|
else if (target == prt)
|
|
rd_switch_reg(name,
|
|
addr+MV88E61XX_PRT_OFST,
|
|
reg, &rdata);
|
|
else
|
|
rd_switch_reg(name, addr, reg, &rdata);
|
|
printf("%s %s %s %02x %s %02x %s %04x\n",
|
|
argv[0], argv[1], argv[2], addr,
|
|
argv[4], reg, argv[6], rdata);
|
|
if (write && argc == 7 && rdata != data)
|
|
return 1;
|
|
}
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
U_BOOT_CMD(mv88e61xx, 8, 0, do_switch,
|
|
"Read or write mv88e61xx switch registers",
|
|
"<ethdevice> dev|port|phy <addr> reg <reg> write <data>\n"
|
|
"<ethdevice> dev|port|phy <addr> reg <reg> read [<data>]\n"
|
|
" - read/write switch device, port or phy at (addr,reg)\n"
|
|
" addr=0..0x1C for dev, 0..5 for port or phy.\n"
|
|
" reg=0..0x1F.\n"
|
|
" data=0..0xFFFF (tested if present against actual read).\n"
|
|
" All numeric parameters are assumed to be hex.\n"
|
|
" <addr> and <<reg> arguments can be ranges (x..y)"
|
|
);
|
|
#endif /* CONFIG_MV88E61XX_CMD */
|