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![Minkyu Kang](/assets/img/avatar_default.png)
move arm/arm/cpu/armv7/s5pc1xx to arch/arm/mach-s5pc1xx Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
328 lines
6.4 KiB
C
328 lines
6.4 KiB
C
/*
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* Copyright (C) 2009 Samsung Electronics
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* Minkyu Kang <mk7.kang@samsung.com>
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* Heungjun Kim <riverful.kim@samsung.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/clk.h>
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#define CLK_M 0
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#define CLK_D 1
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#define CLK_P 2
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#ifndef CONFIG_SYS_CLK_FREQ_C100
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#define CONFIG_SYS_CLK_FREQ_C100 12000000
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#endif
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#ifndef CONFIG_SYS_CLK_FREQ_C110
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#define CONFIG_SYS_CLK_FREQ_C110 24000000
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#endif
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/* s5pc110: return pll clock frequency */
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static unsigned long s5pc100_get_pll_clk(int pllreg)
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{
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struct s5pc100_clock *clk =
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(struct s5pc100_clock *)samsung_get_base_clock();
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unsigned long r, m, p, s, mask, fout;
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unsigned int freq;
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switch (pllreg) {
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case APLL:
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r = readl(&clk->apll_con);
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break;
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case MPLL:
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r = readl(&clk->mpll_con);
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break;
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case EPLL:
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r = readl(&clk->epll_con);
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break;
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case HPLL:
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r = readl(&clk->hpll_con);
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break;
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default:
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printf("Unsupported PLL (%d)\n", pllreg);
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return 0;
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}
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/*
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* APLL_CON: MIDV [25:16]
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* MPLL_CON: MIDV [23:16]
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* EPLL_CON: MIDV [23:16]
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* HPLL_CON: MIDV [23:16]
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*/
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if (pllreg == APLL)
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mask = 0x3ff;
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else
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mask = 0x0ff;
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m = (r >> 16) & mask;
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/* PDIV [13:8] */
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p = (r >> 8) & 0x3f;
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/* SDIV [2:0] */
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s = r & 0x7;
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/* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
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freq = CONFIG_SYS_CLK_FREQ_C100;
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fout = m * (freq / (p * (1 << s)));
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return fout;
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}
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/* s5pc100: return pll clock frequency */
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static unsigned long s5pc110_get_pll_clk(int pllreg)
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{
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struct s5pc110_clock *clk =
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(struct s5pc110_clock *)samsung_get_base_clock();
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unsigned long r, m, p, s, mask, fout;
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unsigned int freq;
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switch (pllreg) {
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case APLL:
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r = readl(&clk->apll_con);
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break;
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case MPLL:
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r = readl(&clk->mpll_con);
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break;
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case EPLL:
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r = readl(&clk->epll_con);
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break;
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case VPLL:
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r = readl(&clk->vpll_con);
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break;
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default:
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printf("Unsupported PLL (%d)\n", pllreg);
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return 0;
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}
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/*
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* APLL_CON: MIDV [25:16]
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* MPLL_CON: MIDV [25:16]
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* EPLL_CON: MIDV [24:16]
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* VPLL_CON: MIDV [24:16]
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*/
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if (pllreg == APLL || pllreg == MPLL)
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mask = 0x3ff;
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else
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mask = 0x1ff;
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m = (r >> 16) & mask;
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/* PDIV [13:8] */
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p = (r >> 8) & 0x3f;
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/* SDIV [2:0] */
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s = r & 0x7;
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freq = CONFIG_SYS_CLK_FREQ_C110;
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if (pllreg == APLL) {
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if (s < 1)
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s = 1;
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/* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
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fout = m * (freq / (p * (1 << (s - 1))));
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} else
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/* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
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fout = m * (freq / (p * (1 << s)));
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return fout;
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}
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/* s5pc110: return ARM clock frequency */
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static unsigned long s5pc110_get_arm_clk(void)
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{
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struct s5pc110_clock *clk =
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(struct s5pc110_clock *)samsung_get_base_clock();
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unsigned long div;
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unsigned long dout_apll, armclk;
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unsigned int apll_ratio;
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div = readl(&clk->div0);
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/* APLL_RATIO: [2:0] */
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apll_ratio = div & 0x7;
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dout_apll = get_pll_clk(APLL) / (apll_ratio + 1);
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armclk = dout_apll;
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return armclk;
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}
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/* s5pc100: return ARM clock frequency */
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static unsigned long s5pc100_get_arm_clk(void)
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{
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struct s5pc100_clock *clk =
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(struct s5pc100_clock *)samsung_get_base_clock();
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unsigned long div;
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unsigned long dout_apll, armclk;
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unsigned int apll_ratio, arm_ratio;
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div = readl(&clk->div0);
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/* ARM_RATIO: [6:4] */
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arm_ratio = (div >> 4) & 0x7;
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/* APLL_RATIO: [0] */
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apll_ratio = div & 0x1;
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dout_apll = get_pll_clk(APLL) / (apll_ratio + 1);
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armclk = dout_apll / (arm_ratio + 1);
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return armclk;
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}
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/* s5pc100: return HCLKD0 frequency */
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static unsigned long get_hclk(void)
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{
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struct s5pc100_clock *clk =
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(struct s5pc100_clock *)samsung_get_base_clock();
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unsigned long hclkd0;
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uint div, d0_bus_ratio;
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div = readl(&clk->div0);
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/* D0_BUS_RATIO: [10:8] */
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d0_bus_ratio = (div >> 8) & 0x7;
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hclkd0 = get_arm_clk() / (d0_bus_ratio + 1);
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return hclkd0;
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}
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/* s5pc100: return PCLKD1 frequency */
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static unsigned long get_pclkd1(void)
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{
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struct s5pc100_clock *clk =
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(struct s5pc100_clock *)samsung_get_base_clock();
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unsigned long d1_bus, pclkd1;
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uint div, d1_bus_ratio, pclkd1_ratio;
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div = readl(&clk->div0);
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/* D1_BUS_RATIO: [14:12] */
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d1_bus_ratio = (div >> 12) & 0x7;
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/* PCLKD1_RATIO: [18:16] */
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pclkd1_ratio = (div >> 16) & 0x7;
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/* ASYNC Mode */
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d1_bus = get_pll_clk(MPLL) / (d1_bus_ratio + 1);
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pclkd1 = d1_bus / (pclkd1_ratio + 1);
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return pclkd1;
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}
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/* s5pc110: return HCLKs frequency */
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static unsigned long get_hclk_sys(int dom)
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{
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struct s5pc110_clock *clk =
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(struct s5pc110_clock *)samsung_get_base_clock();
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unsigned long hclk;
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unsigned int div;
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unsigned int offset;
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unsigned int hclk_sys_ratio;
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if (dom == CLK_M)
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return get_hclk();
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div = readl(&clk->div0);
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/*
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* HCLK_MSYS_RATIO: [10:8]
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* HCLK_DSYS_RATIO: [19:16]
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* HCLK_PSYS_RATIO: [27:24]
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*/
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offset = 8 + (dom << 0x3);
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hclk_sys_ratio = (div >> offset) & 0xf;
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hclk = get_pll_clk(MPLL) / (hclk_sys_ratio + 1);
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return hclk;
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}
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/* s5pc110: return PCLKs frequency */
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static unsigned long get_pclk_sys(int dom)
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{
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struct s5pc110_clock *clk =
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(struct s5pc110_clock *)samsung_get_base_clock();
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unsigned long pclk;
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unsigned int div;
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unsigned int offset;
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unsigned int pclk_sys_ratio;
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div = readl(&clk->div0);
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/*
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* PCLK_MSYS_RATIO: [14:12]
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* PCLK_DSYS_RATIO: [22:20]
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* PCLK_PSYS_RATIO: [30:28]
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*/
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offset = 12 + (dom << 0x3);
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pclk_sys_ratio = (div >> offset) & 0x7;
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pclk = get_hclk_sys(dom) / (pclk_sys_ratio + 1);
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return pclk;
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}
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/* s5pc110: return peripheral clock frequency */
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static unsigned long s5pc110_get_pclk(void)
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{
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return get_pclk_sys(CLK_P);
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}
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/* s5pc100: return peripheral clock frequency */
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static unsigned long s5pc100_get_pclk(void)
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{
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return get_pclkd1();
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}
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/* s5pc1xx: return uart clock frequency */
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static unsigned long s5pc1xx_get_uart_clk(int dev_index)
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{
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if (cpu_is_s5pc110())
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return s5pc110_get_pclk();
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else
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return s5pc100_get_pclk();
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}
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/* s5pc1xx: return pwm clock frequency */
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static unsigned long s5pc1xx_get_pwm_clk(void)
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{
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if (cpu_is_s5pc110())
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return s5pc110_get_pclk();
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else
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return s5pc100_get_pclk();
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}
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unsigned long get_pll_clk(int pllreg)
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{
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if (cpu_is_s5pc110())
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return s5pc110_get_pll_clk(pllreg);
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else
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return s5pc100_get_pll_clk(pllreg);
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}
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unsigned long get_arm_clk(void)
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{
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if (cpu_is_s5pc110())
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return s5pc110_get_arm_clk();
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else
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return s5pc100_get_arm_clk();
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}
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unsigned long get_pwm_clk(void)
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{
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return s5pc1xx_get_pwm_clk();
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}
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unsigned long get_uart_clk(int dev_index)
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{
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return s5pc1xx_get_uart_clk(dev_index);
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}
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void set_mmc_clk(int dev_index, unsigned int div)
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{
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/* Do NOTHING */
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}
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