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https://github.com/brain-hackers/u-boot-brain
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![Hans de Goede](/assets/img/avatar_default.png)
These files are based on the current latest upstream kernel work. The bus_gates bindings may still change, but for u-boot that does not matter as we do not (yet) use any clock info from devicetree for sunxi u-boot. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
596 lines
16 KiB
Plaintext
596 lines
16 KiB
Plaintext
/*
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* Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "skeleton.dtsi"
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/pinctrl/sun4i-a10.h>
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/ {
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interrupt-parent = <&gic>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0>;
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};
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cpu@1 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <1>;
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};
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cpu@2 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <2>;
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};
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cpu@3 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <3>;
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};
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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clock-frequency = <24000000>;
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arm,cpu-registers-not-fw-configured;
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};
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memory {
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reg = <0x40000000 0x80000000>;
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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osc24M: osc24M_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "osc24M";
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};
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osc32k: osc32k_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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clock-output-names = "osc32k";
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};
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pll1: clk@01c20000 {
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#clock-cells = <0>;
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compatible = "allwinner,sun8i-a23-pll1-clk";
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reg = <0x01c20000 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "pll1";
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};
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/* dummy clock until actually implemented */
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pll5: pll5_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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clock-output-names = "pll5";
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};
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pll6: clk@01c20028 {
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#clock-cells = <1>;
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compatible = "allwinner,sun6i-a31-pll6-clk";
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reg = <0x01c20028 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "pll6", "pll6x2", "pll6d2";
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};
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pll8: clk@01c20044 {
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#clock-cells = <1>;
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compatible = "allwinner,sun6i-a31-pll6-clk";
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reg = <0x01c20044 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "pll8", "pll8x2";
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};
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cpu: cpu_clk@01c20050 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-cpu-clk";
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reg = <0x01c20050 0x4>;
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clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
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clock-output-names = "cpu";
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};
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axi: axi_clk@01c20050 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-axi-clk";
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reg = <0x01c20050 0x4>;
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clocks = <&cpu>;
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clock-output-names = "axi";
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};
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ahb1: ahb1_clk@01c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun6i-a31-ahb1-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
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clock-output-names = "ahb1";
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};
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ahb2: ahb2_clk@01c2005c {
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#clock-cells = <0>;
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compatible = "allwinner,sun8i-h3-ahb2-clk";
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reg = <0x01c2005c 0x4>;
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clocks = <&ahb1>, <&pll6 2>;
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clock-output-names = "ahb2";
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};
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apb1: apb1_clk@01c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-apb0-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&ahb1>;
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clock-output-names = "apb1";
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};
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apb2: apb2_clk@01c20058 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-apb1-clk";
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reg = <0x01c20058 0x4>;
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clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
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clock-output-names = "apb2";
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};
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bus_gates: clk@01c20060 {
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#clock-cells = <1>;
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compatible = "allwinner,sun8i-h3-bus-gates-clk";
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reg = <0x01c20060 0x14>;
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clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>;
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clock-names = "ahb1", "ahb2", "apb1", "apb2";
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clock-indices = <5>, <6>, <8>,
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<9>, <10>, <13>,
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<14>, <17>, <18>,
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<19>, <20>,
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<21>, <23>,
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<24>, <25>,
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<26>, <27>,
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<28>, <29>,
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<30>, <31>, <32>,
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<35>, <36>, <37>,
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<40>, <41>, <43>,
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<44>, <52>, <53>,
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<54>, <64>,
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<65>, <69>, <72>,
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<76>, <77>, <78>,
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<96>, <97>, <98>,
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<112>, <113>,
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<114>, <115>, <116>,
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<128>, <135>;
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clock-output-names = "ahb1_ce", "ahb1_dma", "ahb1_mmc0",
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"ahb1_mmc1", "ahb1_mmc2", "ahb1_nand",
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"ahb1_sdram", "ahb2_gmac", "ahb1_ts",
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"ahb1_hstimer", "ahb1_spi0",
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"ahb1_spi1", "ahb1_otg",
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"ahb1_otg_ehci0", "ahb1_ehic1",
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"ahb1_ehic2", "ahb1_ehic3",
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"ahb1_otg_ohci0", "ahb2_ohic1",
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"ahb2_ohic2", "ahb2_ohic3", "ahb1_ve",
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"ahb1_lcd0", "ahb1_lcd1", "ahb1_deint",
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"ahb1_csi", "ahb1_tve", "ahb1_hdmi",
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"ahb1_de", "ahb1_gpu", "ahb1_msgbox",
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"ahb1_spinlock", "apb1_codec",
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"apb1_spdif", "apb1_pio", "apb1_ths",
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"apb1_i2s0", "apb1_i2s1", "apb1_i2s2",
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"apb2_i2c0", "apb2_i2c1", "apb2_i2c2",
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"apb2_uart0", "apb2_uart1",
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"apb2_uart2", "apb2_uart3", "apb2_scr",
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"ahb1_ephy", "ahb1_dbg";
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};
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mmc0_clk: clk@01c20088 {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-mmc-clk";
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reg = <0x01c20088 0x4>;
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clocks = <&osc24M>, <&pll6 0>, <&pll8 0>;
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clock-output-names = "mmc0",
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"mmc0_output",
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"mmc0_sample";
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};
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mmc1_clk: clk@01c2008c {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-mmc-clk";
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reg = <0x01c2008c 0x4>;
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clocks = <&osc24M>, <&pll6 0>, <&pll8 0>;
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clock-output-names = "mmc1",
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"mmc1_output",
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"mmc1_sample";
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};
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mmc2_clk: clk@01c20090 {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-mmc-clk";
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reg = <0x01c20090 0x4>;
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clocks = <&osc24M>, <&pll6 0>, <&pll8 0>;
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clock-output-names = "mmc2",
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"mmc2_output",
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"mmc2_sample";
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};
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usb_clk: clk@01c200cc {
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#clock-cells = <1>;
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#reset-cells = <1>;
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compatible = "allwinner,sun8i-h3-usb-clk";
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reg = <0x01c200cc 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "usb_phy0", "usb_phy1",
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"usb_phy2", "usb_phy3",
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"usb_ohci0", "usb_ohci1",
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"usb_ohci2", "usb_ohci3";
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};
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mbus_clk: clk@01c2015c {
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#clock-cells = <0>;
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compatible = "allwinner,sun8i-a23-mbus-clk";
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reg = <0x01c2015c 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5>;
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clock-output-names = "mbus";
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};
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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dma: dma-controller@01c02000 {
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compatible = "allwinner,sun8i-h3-dma";
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reg = <0x01c02000 0x1000>;
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interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bus_gates 6>;
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resets = <&bus_rst 6>;
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#dma-cells = <1>;
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};
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mmc0: mmc@01c0f000 {
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compatible = "allwinner,sun5i-a13-mmc";
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reg = <0x01c0f000 0x1000>;
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clocks = <&bus_gates 8>,
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<&mmc0_clk 0>,
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<&mmc0_clk 1>,
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<&mmc0_clk 2>;
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clock-names = "ahb",
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"mmc",
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"output",
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"sample";
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resets = <&bus_rst 8>;
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reset-names = "ahb";
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interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mmc1: mmc@01c10000 {
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compatible = "allwinner,sun5i-a13-mmc";
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reg = <0x01c10000 0x1000>;
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clocks = <&bus_gates 9>,
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<&mmc1_clk 0>,
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<&mmc1_clk 1>,
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<&mmc1_clk 2>;
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clock-names = "ahb",
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"mmc",
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"output",
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"sample";
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resets = <&bus_rst 9>;
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reset-names = "ahb";
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interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mmc2: mmc@01c11000 {
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compatible = "allwinner,sun5i-a13-mmc";
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reg = <0x01c11000 0x1000>;
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clocks = <&bus_gates 10>,
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<&mmc2_clk 0>,
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<&mmc2_clk 1>,
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<&mmc2_clk 2>;
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clock-names = "ahb",
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"mmc",
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"output",
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"sample";
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resets = <&bus_rst 10>;
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reset-names = "ahb";
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interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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usbphy: phy@01c19400 {
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compatible = "allwinner,sun8i-h3-usb-phy";
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reg = <0x01c19400 0x2c>,
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<0x01c1a800 0x4>,
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<0x01c1b800 0x4>,
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<0x01c1c800 0x4>,
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<0x01c1d800 0x4>;
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reg-names = "phy_ctrl",
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"pmu0",
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"pmu1",
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"pmu2",
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"pmu3";
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clocks = <&usb_clk 8>,
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<&usb_clk 9>,
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<&usb_clk 10>,
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<&usb_clk 11>;
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clock-names = "usb0_phy",
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"usb1_phy",
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"usb2_phy",
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"usb3_phy";
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resets = <&usb_clk 0>,
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<&usb_clk 1>,
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<&usb_clk 2>,
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<&usb_clk 3>;
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reset-names = "usb0_reset",
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"usb1_reset",
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"usb2_reset",
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"usb3_reset";
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status = "disabled";
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#phy-cells = <1>;
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};
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ehci1: usb@01c1b000 {
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compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
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reg = <0x01c1b000 0x100>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bus_gates 25>, <&bus_gates 29>;
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resets = <&bus_rst 25>, <&bus_rst 29>;
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phys = <&usbphy 1>;
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phy-names = "usb";
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status = "disabled";
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};
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ohci1: usb@01c1b400 {
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compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
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reg = <0x01c1b400 0x100>;
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bus_gates 29>, <&bus_gates 25>,
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<&usb_clk 17>;
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resets = <&bus_rst 29>, <&bus_rst 25>;
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phys = <&usbphy 1>;
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phy-names = "usb";
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status = "disabled";
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};
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ehci2: usb@01c1c000 {
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compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
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reg = <0x01c1c000 0x100>;
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bus_gates 26>, <&bus_gates 30>;
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resets = <&bus_rst 26>, <&bus_rst 30>;
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phys = <&usbphy 2>;
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phy-names = "usb";
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status = "disabled";
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};
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ohci2: usb@01c1c400 {
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compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
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reg = <0x01c1c400 0x100>;
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interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bus_gates 30>, <&bus_gates 26>,
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<&usb_clk 18>;
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resets = <&bus_rst 30>, <&bus_rst 26>;
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phys = <&usbphy 2>;
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phy-names = "usb";
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status = "disabled";
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};
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ehci3: usb@01c1d000 {
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compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
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reg = <0x01c1d000 0x100>;
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interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bus_gates 27>, <&bus_gates 31>;
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resets = <&bus_rst 27>, <&bus_rst 31>;
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phys = <&usbphy 3>;
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phy-names = "usb";
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status = "disabled";
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};
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ohci3: usb@01c1d400 {
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compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
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reg = <0x01c1d400 0x100>;
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interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bus_gates 31>, <&bus_gates 27>,
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<&usb_clk 19>;
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resets = <&bus_rst 31>, <&bus_rst 27>;
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phys = <&usbphy 3>;
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phy-names = "usb";
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|
status = "disabled";
|
|
};
|
|
|
|
pio: pinctrl@01c20800 {
|
|
compatible = "allwinner,sun8i-h3-pinctrl";
|
|
reg = <0x01c20800 0x400>;
|
|
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&bus_gates 69>;
|
|
gpio-controller;
|
|
#gpio-cells = <3>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
|
|
uart0_pins_a: uart0@0 {
|
|
allwinner,pins = "PA4", "PA5";
|
|
allwinner,function = "uart0";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
mmc0_pins_a: mmc0@0 {
|
|
allwinner,pins = "PF0", "PF1", "PF2", "PF3",
|
|
"PF4", "PF5";
|
|
allwinner,function = "mmc0";
|
|
allwinner,drive = <SUN4I_PINCTRL_30_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
|
|
mmc0_cd_pin: mmc0_cd_pin@0 {
|
|
allwinner,pins = "PF6";
|
|
allwinner,function = "gpio_in";
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
|
|
};
|
|
|
|
mmc1_pins_a: mmc1@0 {
|
|
allwinner,pins = "PG0", "PG1", "PG2", "PG3",
|
|
"PG4", "PG5";
|
|
allwinner,function = "mmc1";
|
|
allwinner,drive = <SUN4I_PINCTRL_30_MA>;
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
};
|
|
};
|
|
|
|
bus_rst: reset@01c202c0 {
|
|
#reset-cells = <1>;
|
|
compatible = "allwinner,sun8i-h3-bus-reset";
|
|
reg = <0x01c202c0 0x1c>;
|
|
};
|
|
|
|
timer@01c20c00 {
|
|
compatible = "allwinner,sun4i-a10-timer";
|
|
reg = <0x01c20c00 0xa0>;
|
|
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&osc24M>;
|
|
};
|
|
|
|
wdt0: watchdog@01c20ca0 {
|
|
compatible = "allwinner,sun6i-a31-wdt";
|
|
reg = <0x01c20ca0 0x20>;
|
|
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
uart0: serial@01c28000 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c28000 0x400>;
|
|
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&bus_gates 112>;
|
|
resets = <&bus_rst 144>;
|
|
dmas = <&dma 6>, <&dma 6>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart1: serial@01c28400 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c28400 0x400>;
|
|
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&bus_gates 113>;
|
|
resets = <&bus_rst 145>;
|
|
dmas = <&dma 7>, <&dma 7>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@01c28800 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c28800 0x400>;
|
|
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&bus_gates 114>;
|
|
resets = <&bus_rst 146>;
|
|
dmas = <&dma 8>, <&dma 8>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart3: serial@01c28c00 {
|
|
compatible = "snps,dw-apb-uart";
|
|
reg = <0x01c28c00 0x400>;
|
|
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&bus_gates 115>;
|
|
resets = <&bus_rst 147>;
|
|
dmas = <&dma 9>, <&dma 9>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
gic: interrupt-controller@01c81000 {
|
|
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
|
|
reg = <0x01c81000 0x1000>,
|
|
<0x01c82000 0x1000>,
|
|
<0x01c84000 0x2000>,
|
|
<0x01c86000 0x2000>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
|
};
|
|
|
|
rtc: rtc@01f00000 {
|
|
compatible = "allwinner,sun6i-a31-rtc";
|
|
reg = <0x01f00000 0x54>;
|
|
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
};
|