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https://github.com/brain-hackers/u-boot-brain
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170817a497
The DRAM controller in the Allwinner H5 SoC is again very similar to the one in the H3 and A64. Based on the existing socid parameter, add support for this controller by reusing the bulk of the code and only deviating where needed. These new bits set or cleared here and there have been mostly found by looking at DRAM register dumps after using the H5 boot0 and comparing them to what we set in the code. So for now it's mostly unclear what those bits actually mean - hence the missing names and comments. Also add the delay line parameters taken from the boot0 and libdram disassembly. Register setup differences between H5 and H3 are courtesy of Jens Kuske. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
21 lines
358 B
C
21 lines
358 B
C
/*
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* (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _SUNXI_CPU_H
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#define _SUNXI_CPU_H
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#if defined(CONFIG_MACH_SUN9I)
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#include <asm/arch/cpu_sun9i.h>
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#else
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#include <asm/arch/cpu_sun4i.h>
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#endif
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#define SOCID_A64 0x1689
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#define SOCID_H3 0x1680
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#define SOCID_H5 0x1718
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#endif /* _SUNXI_CPU_H */
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