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![Tom Rini](/assets/img/avatar_default.png)
This series moves the CONFIG_SYS_CACHELINE_SIZE. First, in nearly all cases we are mirroring the values used by the Linux Kernel here. Also, so long as (and in this case, it is true) we implement flushes in hunks that are no larger than the smallest implementation (and given that we mirror the Linux Kernel, again we are fine) it is OK to align higher. The biggest changes here are that we always use 64 bytes for CPU_V7 even if for example the underlying core is only 32 bytes (this mirrors Linux). Second, we say ARM64 uses 64 bytes not 128 (as found in the Linux Kernel) as we do not need multi-platform support (to this degree) and only the Cavium ThunderX 88xx series has a use for such large alignment. Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Prafulla Wadaskar <prafulla@marvell.com> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Stefan Roese <sr@denx.de> Cc: Nagendra T S <nagendra@mistralsolutions.com> Cc: Vaibhav Hiremath <hvaibhav@ti.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com> Cc: Steve Rae <steve.rae@raedomain.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Stefan Agner <stefan.agner@toradex.com> Acked-by: Heiko Schocher <hs@denx.de> Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Cc: Peter Griffin <peter.griffin@linaro.org> Acked-by: Paul Kocialkowski <contact@paulk.fr> Cc: Anatolij Gustschin <agust@denx.de> Acked-by: "Pali Rohár" <pali.rohar@gmail.com> Cc: Adam Ford <aford173@gmail.com> Cc: Steve Sakoman <sakoman@gmail.com> Cc: Grazvydas Ignotas <notasas@gmail.com> Cc: Nishanth Menon <nm@ti.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Robert Baldyga <r.baldyga@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Thomas Weber <weber@corscience.de> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: David Feng <fenghua@phytium.com.cn> Cc: Alison Wang <b18965@freescale.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Simon Glass <sjg@chromium.org> Cc: York Sun <york.sun@nxp.com> Cc: Shengzhou Liu <Shengzhou.Liu@nxp.com> Cc: Mingkai Hu <mingkai.hu@nxp.com> Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Cc: Aneesh Bansal <aneesh.bansal@freescale.com> Cc: Saksham Jain <saksham.jain@nxp.com> Cc: Qianyu Gong <qianyu.gong@nxp.com> Cc: Wang Dongsheng <dongsheng.wang@nxp.com> Cc: Alex Porosanu <alexandru.porosanu@freescale.com> Cc: Hongbo Zhang <hongbo.zhang@nxp.com> Cc: tang yuantian <Yuantian.Tang@freescale.com> Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com> Cc: Josh Wu <josh.wu@atmel.com> Cc: Bo Shen <voice.shen@atmel.com> Cc: Viresh Kumar <viresh.kumar@linaro.org> Cc: Hannes Schmelzer <oe5hpm@oevsv.at> Cc: Thomas Chou <thomas@wytron.com.tw> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Sam Protsenko <semen.protsenko@linaro.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Christophe Ricard <christophe-h.ricard@st.com> Cc: Anand Moon <linux.amoon@gmail.com> Cc: Beniamino Galvani <b.galvani@gmail.com> Cc: Carlo Caione <carlo@endlessm.com> Cc: huang lin <hl@rock-chips.com> Cc: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Cc: Xu Ziyuan <xzy.xu@rock-chips.com> Cc: "jk.kernel@gmail.com" <jk.kernel@gmail.com> Cc: "Ariel D'Alessandro" <ariel@vanguardiasur.com.ar> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Samuel Egli <samuel.egli@siemens.com> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Ian Campbell <ijc@hellion.org.uk> Cc: Siarhei Siamashka <siarhei.siamashka@gmail.com> Cc: Boris Brezillon <boris.brezillon@free-electrons.com> Cc: Andre Przywara <andre.przywara@arm.com> Cc: Bernhard Nortmann <bernhard.nortmann@web.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Ben Whitten <ben.whitten@gmail.com> Cc: Tom Warren <twarren@nvidia.com> Cc: Alexander Graf <agraf@suse.de> Cc: Sekhar Nori <nsekhar@ti.com> Cc: Vitaly Andrianov <vitalya@ti.com> Cc: "Andrew F. Davis" <afd@ti.com> Cc: Murali Karicheri <m-karicheri2@ti.com> Cc: Carlos Hernandez <ceh@ti.com> Cc: Ladislav Michl <ladis@linux-mips.org> Cc: Ash Charles <ashcharles@gmail.com> Cc: Mugunthan V N <mugunthanvnm@ti.com> Cc: Daniel Allred <d-allred@ti.com> Cc: Gong Qianyu <Qianyu.Gong@freescale.com> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Chin Liang See <clsee@altera.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Paul Kocialkowski <contact@paulk.fr>
112 lines
2.2 KiB
C
112 lines
2.2 KiB
C
/*
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* (C) Copyright 2004 Texas Insturments
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2002
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* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* CPU specific code
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/system.h>
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static void cache_flush(void);
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int cleanup_before_linux (void)
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{
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/*
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* this function is called just before we call linux
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* it prepares the processor for linux
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*
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* we turn off caches etc ...
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*/
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disable_interrupts ();
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/* turn off I/D-cache */
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icache_disable();
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dcache_disable();
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/* flush I/D-cache */
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cache_flush();
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return 0;
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}
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static void cache_flush(void)
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{
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unsigned long i = 0;
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/* clean entire data cache */
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asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (i));
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/* invalidate both caches and flush btb */
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asm volatile("mcr p15, 0, %0, c7, c7, 0" : : "r" (i));
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/* mem barrier to sync things */
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asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (i));
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}
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#ifndef CONFIG_SYS_DCACHE_OFF
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void invalidate_dcache_all(void)
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{
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asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
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}
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void flush_dcache_all(void)
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{
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asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (0));
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asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
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}
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void invalidate_dcache_range(unsigned long start, unsigned long stop)
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{
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if (!check_cache_range(start, stop))
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return;
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while (start < stop) {
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asm volatile("mcr p15, 0, %0, c7, c6, 1" : : "r" (start));
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start += CONFIG_SYS_CACHELINE_SIZE;
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}
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}
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void flush_dcache_range(unsigned long start, unsigned long stop)
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{
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if (!check_cache_range(start, stop))
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return;
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while (start < stop) {
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asm volatile("mcr p15, 0, %0, c7, c14, 1" : : "r" (start));
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start += CONFIG_SYS_CACHELINE_SIZE;
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}
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asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
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}
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#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
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void invalidate_dcache_all(void)
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{
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}
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void flush_dcache_all(void)
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{
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}
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#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
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#if !defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF)
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void enable_caches(void)
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{
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#ifndef CONFIG_SYS_ICACHE_OFF
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icache_enable();
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#endif
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#ifndef CONFIG_SYS_DCACHE_OFF
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dcache_enable();
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#endif
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}
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#endif
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