mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-07 11:46:17 +09:00
0d47bc7056
Add initial clock driver for Allwinner A64. Implement USB clock enable and disable functions for OHCI, EHCI, OTG and USBPHY gate and clock registers via ccu clk gate table. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
38 lines
1.3 KiB
Makefile
38 lines
1.3 KiB
Makefile
# SPDX-License-Identifier: GPL-2.0+
|
|
#
|
|
# Copyright (c) 2015 Google, Inc
|
|
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
#
|
|
|
|
obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o clk_fixed_rate.o
|
|
|
|
obj-y += imx/
|
|
obj-y += tegra/
|
|
obj-$(CONFIG_ARCH_ASPEED) += aspeed/
|
|
obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
|
|
obj-$(CONFIG_ARCH_MESON) += clk_meson.o clk_meson_axg.o
|
|
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
|
|
obj-$(CONFIG_ARCH_SOCFPGA) += altera/
|
|
obj-$(CONFIG_CLK_AT91) += at91/
|
|
obj-$(CONFIG_CLK_MVEBU) += mvebu/
|
|
obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o
|
|
obj-$(CONFIG_CLK_BOSTON) += clk_boston.o
|
|
obj-$(CONFIG_CLK_EXYNOS) += exynos/
|
|
obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o
|
|
obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o
|
|
obj-$(CONFIG_CLK_OWL) += owl/
|
|
obj-$(CONFIG_CLK_RENESAS) += renesas/
|
|
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
|
|
obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o
|
|
obj-$(CONFIG_CLK_STM32MP1) += clk_stm32mp1.o
|
|
obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
|
|
obj-$(CONFIG_CLK_VEXPRESS_OSC) += clk_vexpress_osc.o
|
|
obj-$(CONFIG_CLK_ZYNQ) += clk_zynq.o
|
|
obj-$(CONFIG_CLK_ZYNQMP) += clk_zynqmp.o
|
|
obj-$(CONFIG_ICS8N3QV01) += ics8n3qv01.o
|
|
obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
|
|
obj-$(CONFIG_SANDBOX) += clk_sandbox.o
|
|
obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o
|
|
obj-$(CONFIG_STM32H7) += clk_stm32h7.o
|
|
obj-$(CONFIG_CLK_TI_SCI) += clk-ti-sci.o
|