mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-09 20:56:16 +09:00
bc6bbd6be8
Issue: Address masking doesn't work properly. When sum of the base address, defined by BA, and memory bank size, defined by AM, exceeds 4GB (0xffff_ffff) then AMASKn[AM] doesn't mask CSPRn[BA] bits. Impact: This will impact booting when we are reprogramming CSPR0(BA) and AMASK0(AMASK) while executing from NOR Flash. Workaround: Re-programming of CSPR(BA) and AMASK is done while not executing from NOR Flash. The code which programs the BA and AMASK is executed from L2-SRAM. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
86 lines
3.0 KiB
C
86 lines
3.0 KiB
C
/*
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* Copyright 2010-2011 Freescale Semiconductor, Inc.
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* Author: Dipen Dudhat <dipen.dudhat@freescale.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/fsl_ifc.h>
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void print_ifc_regs(void)
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{
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int i, j;
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printf("IFC Controller Registers\n");
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for (i = 0; i < FSL_IFC_BANK_COUNT; i++) {
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printf("CSPR%d:0x%08X\tAMASK%d:0x%08X\tCSOR%d:0x%08X\n",
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i, get_ifc_cspr(i), i, get_ifc_amask(i),
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i, get_ifc_csor(i));
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for (j = 0; j < 4; j++)
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printf("IFC_FTIM%d:0x%08X\n", j, get_ifc_ftim(i, j));
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}
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}
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void init_early_memctl_regs(void)
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{
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#if defined(CONFIG_SYS_CSPR0) && defined(CONFIG_SYS_CSOR0)
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set_ifc_ftim(IFC_CS0, IFC_FTIM0, CONFIG_SYS_CS0_FTIM0);
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set_ifc_ftim(IFC_CS0, IFC_FTIM1, CONFIG_SYS_CS0_FTIM1);
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set_ifc_ftim(IFC_CS0, IFC_FTIM2, CONFIG_SYS_CS0_FTIM2);
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set_ifc_ftim(IFC_CS0, IFC_FTIM3, CONFIG_SYS_CS0_FTIM3);
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#if !defined(CONFIG_SYS_FSL_ERRATUM_IFC_A003399) || defined(CONFIG_SYS_RAMBOOT)
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set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0);
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set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0);
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set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0);
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#endif
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#endif
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#if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1)
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set_ifc_ftim(IFC_CS1, IFC_FTIM0, CONFIG_SYS_CS1_FTIM0);
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set_ifc_ftim(IFC_CS1, IFC_FTIM1, CONFIG_SYS_CS1_FTIM1);
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set_ifc_ftim(IFC_CS1, IFC_FTIM2, CONFIG_SYS_CS1_FTIM2);
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set_ifc_ftim(IFC_CS1, IFC_FTIM3, CONFIG_SYS_CS1_FTIM3);
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set_ifc_csor(IFC_CS1, CONFIG_SYS_CSOR1);
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set_ifc_amask(IFC_CS1, CONFIG_SYS_AMASK1);
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set_ifc_cspr(IFC_CS1, CONFIG_SYS_CSPR1);
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#endif
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#if defined(CONFIG_SYS_CSPR2) && defined(CONFIG_SYS_CSOR2)
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set_ifc_ftim(IFC_CS2, IFC_FTIM0, CONFIG_SYS_CS2_FTIM0);
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set_ifc_ftim(IFC_CS2, IFC_FTIM1, CONFIG_SYS_CS2_FTIM1);
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set_ifc_ftim(IFC_CS2, IFC_FTIM2, CONFIG_SYS_CS2_FTIM2);
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set_ifc_ftim(IFC_CS2, IFC_FTIM3, CONFIG_SYS_CS2_FTIM3);
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set_ifc_csor(IFC_CS2, CONFIG_SYS_CSOR2);
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set_ifc_amask(IFC_CS2, CONFIG_SYS_AMASK2);
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set_ifc_cspr(IFC_CS2, CONFIG_SYS_CSPR2);
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#endif
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#if defined(CONFIG_SYS_CSPR3) && defined(CONFIG_SYS_CSOR3)
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set_ifc_ftim(IFC_CS3, IFC_FTIM0, CONFIG_SYS_CS3_FTIM0);
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set_ifc_ftim(IFC_CS3, IFC_FTIM1, CONFIG_SYS_CS3_FTIM1);
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set_ifc_ftim(IFC_CS3, IFC_FTIM2, CONFIG_SYS_CS3_FTIM2);
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set_ifc_ftim(IFC_CS3, IFC_FTIM3, CONFIG_SYS_CS3_FTIM3);
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set_ifc_cspr(IFC_CS3, CONFIG_SYS_CSPR3);
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set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3);
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set_ifc_csor(IFC_CS3, CONFIG_SYS_CSOR3);
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#endif
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}
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