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https://github.com/brain-hackers/u-boot-brain
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d29d17d7ba
Unified DDR driver is maintained for better performance, robustness and bug fixes. Upgrading to use unified DDR driver for MPC83xx takes advantage of overall improvement. It requires changes for board files to customize platform-dependent parameters. To utilize the unified DDR driver, a board needs to define CONFIG_FSL_DDRx in the header file. No more boards will be accepted without such definition. Note: the workaround for erratum DDR6 for the very old MPC834x Rev 1.0/1.1 and MPC8360 Rev 1.1/1.2 parts is not migrated to unified driver. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
396 lines
12 KiB
C
396 lines
12 KiB
C
/*
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* Copyright (C) 2007-2011 Freescale Semiconductor, Inc.
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*
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* Dave Liu <daveliu@freescale.com>
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* based on the contribution of Marian Balakowicz <m8@semihalf.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#include <common.h>
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#include <mpc83xx.h>
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#include <command.h>
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#if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD)
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void ecc_print_status(void)
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{
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immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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#ifdef CONFIG_FSL_DDR2
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ccsr_ddr_t *ddr = &immap->ddr;
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#else
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ddr83xx_t *ddr = &immap->ddr;
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#endif
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printf("\nECC mode: %s\n\n",
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(ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF");
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/* Interrupts */
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printf("Memory Error Interrupt Enable:\n");
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printf(" Multiple-Bit Error Interrupt Enable: %d\n",
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(ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0);
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printf(" Single-Bit Error Interrupt Enable: %d\n",
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(ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0);
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printf(" Memory Select Error Interrupt Enable: %d\n\n",
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(ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0);
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/* Error disable */
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printf("Memory Error Disable:\n");
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printf(" Multiple-Bit Error Disable: %d\n",
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(ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0);
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printf(" Sinle-Bit Error Disable: %d\n",
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(ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0);
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printf(" Memory Select Error Disable: %d\n\n",
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(ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0);
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/* Error injection */
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printf("Memory Data Path Error Injection Mask High/Low: %08x %08x\n",
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ddr->data_err_inject_hi, ddr->data_err_inject_lo);
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printf("Memory Data Path Error Injection Mask ECC:\n");
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printf(" ECC Mirror Byte: %d\n",
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(ddr->ecc_err_inject & ECC_ERR_INJECT_EMB) ? 1 : 0);
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printf(" ECC Injection Enable: %d\n",
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(ddr->ecc_err_inject & ECC_ERR_INJECT_EIEN) ? 1 : 0);
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printf(" ECC Error Injection Mask: 0x%02x\n\n",
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ddr->ecc_err_inject & ECC_ERR_INJECT_EEIM);
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/* SBE counter/threshold */
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printf("Memory Single-Bit Error Management (0..255):\n");
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printf(" Single-Bit Error Threshold: %d\n",
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(ddr->err_sbe & ECC_ERROR_MAN_SBET) >> ECC_ERROR_MAN_SBET_SHIFT);
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printf(" Single-Bit Error Counter: %d\n\n",
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(ddr->err_sbe & ECC_ERROR_MAN_SBEC) >> ECC_ERROR_MAN_SBEC_SHIFT);
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/* Error detect */
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printf("Memory Error Detect:\n");
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printf(" Multiple Memory Errors: %d\n",
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(ddr->err_detect & ECC_ERROR_DETECT_MME) ? 1 : 0);
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printf(" Multiple-Bit Error: %d\n",
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(ddr->err_detect & ECC_ERROR_DETECT_MBE) ? 1 : 0);
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printf(" Single-Bit Error: %d\n",
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(ddr->err_detect & ECC_ERROR_DETECT_SBE) ? 1 : 0);
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printf(" Memory Select Error: %d\n\n",
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(ddr->err_detect & ECC_ERROR_DETECT_MSE) ? 1 : 0);
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/* Capture data */
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printf("Memory Error Address Capture: 0x%08x\n", ddr->capture_address);
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printf("Memory Data Path Read Capture High/Low: %08x %08x\n",
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ddr->capture_data_hi, ddr->capture_data_lo);
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printf("Memory Data Path Read Capture ECC: 0x%02x\n\n",
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ddr->capture_ecc & CAPTURE_ECC_ECE);
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printf("Memory Error Attributes Capture:\n");
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printf(" Data Beat Number: %d\n",
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(ddr->capture_attributes & ECC_CAPT_ATTR_BNUM) >>
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ECC_CAPT_ATTR_BNUM_SHIFT);
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printf(" Transaction Size: %d\n",
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(ddr->capture_attributes & ECC_CAPT_ATTR_TSIZ) >>
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ECC_CAPT_ATTR_TSIZ_SHIFT);
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printf(" Transaction Source: %d\n",
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(ddr->capture_attributes & ECC_CAPT_ATTR_TSRC) >>
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ECC_CAPT_ATTR_TSRC_SHIFT);
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printf(" Transaction Type: %d\n",
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(ddr->capture_attributes & ECC_CAPT_ATTR_TTYP) >>
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ECC_CAPT_ATTR_TTYP_SHIFT);
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printf(" Error Information Valid: %d\n\n",
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ddr->capture_attributes & ECC_CAPT_ATTR_VLD);
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}
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int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
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{
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immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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#ifdef CONFIG_FSL_DDR2
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ccsr_ddr_t *ddr = &immap->ddr;
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#else
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ddr83xx_t *ddr = &immap->ddr;
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#endif
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volatile u32 val;
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u64 *addr;
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u32 count;
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register u64 *i;
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u32 ret[2];
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u32 pattern[2];
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u32 writeback[2];
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/* The pattern is written into memory to generate error */
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pattern[0] = 0xfedcba98UL;
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pattern[1] = 0x76543210UL;
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/* After injecting error, re-initialize the memory with the value */
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writeback[0] = 0x01234567UL;
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writeback[1] = 0x89abcdefUL;
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if (argc > 4)
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return cmd_usage(cmdtp);
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if (argc == 2) {
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if (strcmp(argv[1], "status") == 0) {
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ecc_print_status();
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return 0;
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} else if (strcmp(argv[1], "captureclear") == 0) {
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ddr->capture_address = 0;
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ddr->capture_data_hi = 0;
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ddr->capture_data_lo = 0;
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ddr->capture_ecc = 0;
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ddr->capture_attributes = 0;
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return 0;
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}
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}
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if (argc == 3) {
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if (strcmp(argv[1], "sbecnt") == 0) {
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val = simple_strtoul(argv[2], NULL, 10);
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if (val > 255) {
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printf("Incorrect Counter value, "
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"should be 0..255\n");
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return 1;
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}
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val = (val << ECC_ERROR_MAN_SBEC_SHIFT);
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val |= (ddr->err_sbe & ECC_ERROR_MAN_SBET);
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ddr->err_sbe = val;
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return 0;
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} else if (strcmp(argv[1], "sbethr") == 0) {
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val = simple_strtoul(argv[2], NULL, 10);
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if (val > 255) {
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printf("Incorrect Counter value, "
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"should be 0..255\n");
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return 1;
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}
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val = (val << ECC_ERROR_MAN_SBET_SHIFT);
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val |= (ddr->err_sbe & ECC_ERROR_MAN_SBEC);
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ddr->err_sbe = val;
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return 0;
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} else if (strcmp(argv[1], "errdisable") == 0) {
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val = ddr->err_disable;
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if (strcmp(argv[2], "+sbe") == 0) {
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val |= ECC_ERROR_DISABLE_SBED;
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} else if (strcmp(argv[2], "+mbe") == 0) {
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val |= ECC_ERROR_DISABLE_MBED;
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} else if (strcmp(argv[2], "+mse") == 0) {
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val |= ECC_ERROR_DISABLE_MSED;
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} else if (strcmp(argv[2], "+all") == 0) {
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val |= (ECC_ERROR_DISABLE_SBED |
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ECC_ERROR_DISABLE_MBED |
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ECC_ERROR_DISABLE_MSED);
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} else if (strcmp(argv[2], "-sbe") == 0) {
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val &= ~ECC_ERROR_DISABLE_SBED;
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} else if (strcmp(argv[2], "-mbe") == 0) {
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val &= ~ECC_ERROR_DISABLE_MBED;
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} else if (strcmp(argv[2], "-mse") == 0) {
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val &= ~ECC_ERROR_DISABLE_MSED;
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} else if (strcmp(argv[2], "-all") == 0) {
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val &= ~(ECC_ERROR_DISABLE_SBED |
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ECC_ERROR_DISABLE_MBED |
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ECC_ERROR_DISABLE_MSED);
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} else {
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printf("Incorrect err_disable field\n");
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return 1;
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}
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ddr->err_disable = val;
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__asm__ __volatile__("sync");
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__asm__ __volatile__("isync");
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return 0;
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} else if (strcmp(argv[1], "errdetectclr") == 0) {
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val = ddr->err_detect;
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if (strcmp(argv[2], "mme") == 0) {
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val |= ECC_ERROR_DETECT_MME;
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} else if (strcmp(argv[2], "sbe") == 0) {
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val |= ECC_ERROR_DETECT_SBE;
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} else if (strcmp(argv[2], "mbe") == 0) {
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val |= ECC_ERROR_DETECT_MBE;
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} else if (strcmp(argv[2], "mse") == 0) {
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val |= ECC_ERROR_DETECT_MSE;
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} else if (strcmp(argv[2], "all") == 0) {
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val |= (ECC_ERROR_DETECT_MME |
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ECC_ERROR_DETECT_MBE |
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ECC_ERROR_DETECT_SBE |
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ECC_ERROR_DETECT_MSE);
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} else {
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printf("Incorrect err_detect field\n");
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return 1;
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}
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ddr->err_detect = val;
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return 0;
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} else if (strcmp(argv[1], "injectdatahi") == 0) {
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val = simple_strtoul(argv[2], NULL, 16);
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ddr->data_err_inject_hi = val;
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return 0;
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} else if (strcmp(argv[1], "injectdatalo") == 0) {
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val = simple_strtoul(argv[2], NULL, 16);
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ddr->data_err_inject_lo = val;
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return 0;
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} else if (strcmp(argv[1], "injectecc") == 0) {
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val = simple_strtoul(argv[2], NULL, 16);
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if (val > 0xff) {
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printf("Incorrect ECC inject mask, "
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"should be 0x00..0xff\n");
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return 1;
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}
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val |= (ddr->ecc_err_inject & ~ECC_ERR_INJECT_EEIM);
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ddr->ecc_err_inject = val;
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return 0;
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} else if (strcmp(argv[1], "inject") == 0) {
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val = ddr->ecc_err_inject;
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if (strcmp(argv[2], "en") == 0)
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val |= ECC_ERR_INJECT_EIEN;
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else if (strcmp(argv[2], "dis") == 0)
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val &= ~ECC_ERR_INJECT_EIEN;
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else
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printf("Incorrect command\n");
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ddr->ecc_err_inject = val;
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__asm__ __volatile__("sync");
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__asm__ __volatile__("isync");
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return 0;
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} else if (strcmp(argv[1], "mirror") == 0) {
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val = ddr->ecc_err_inject;
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if (strcmp(argv[2], "en") == 0)
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val |= ECC_ERR_INJECT_EMB;
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else if (strcmp(argv[2], "dis") == 0)
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val &= ~ECC_ERR_INJECT_EMB;
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else
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printf("Incorrect command\n");
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ddr->ecc_err_inject = val;
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return 0;
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}
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}
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if (argc == 4) {
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if (strcmp(argv[1], "testdw") == 0) {
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addr = (u64 *) simple_strtoul(argv[2], NULL, 16);
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count = simple_strtoul(argv[3], NULL, 16);
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if ((u32) addr % 8) {
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printf("Address not alligned on "
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"double word boundary\n");
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return 1;
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}
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disable_interrupts();
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for (i = addr; i < addr + count; i++) {
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/* enable injects */
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ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
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__asm__ __volatile__("sync");
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__asm__ __volatile__("isync");
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/* write memory location injecting errors */
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ppcDWstore((u32 *) i, pattern);
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__asm__ __volatile__("sync");
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/* disable injects */
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ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
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__asm__ __volatile__("sync");
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__asm__ __volatile__("isync");
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/* read data, this generates ECC error */
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ppcDWload((u32 *) i, ret);
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__asm__ __volatile__("sync");
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/* re-initialize memory, double word write the location again,
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* generates new ECC code this time */
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ppcDWstore((u32 *) i, writeback);
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__asm__ __volatile__("sync");
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}
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enable_interrupts();
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return 0;
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}
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if (strcmp(argv[1], "testword") == 0) {
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addr = (u64 *) simple_strtoul(argv[2], NULL, 16);
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count = simple_strtoul(argv[3], NULL, 16);
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if ((u32) addr % 8) {
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printf("Address not alligned on "
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"double word boundary\n");
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return 1;
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}
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disable_interrupts();
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for (i = addr; i < addr + count; i++) {
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/* enable injects */
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ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
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__asm__ __volatile__("sync");
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__asm__ __volatile__("isync");
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/* write memory location injecting errors */
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*(u32 *) i = 0xfedcba98UL;
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__asm__ __volatile__("sync");
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/* sub double word write,
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* bus will read-modify-write,
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* generates ECC error */
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*((u32 *) i + 1) = 0x76543210UL;
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__asm__ __volatile__("sync");
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/* disable injects */
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ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
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__asm__ __volatile__("sync");
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__asm__ __volatile__("isync");
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/* re-initialize memory,
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* double word write the location again,
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* generates new ECC code this time */
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ppcDWstore((u32 *) i, writeback);
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__asm__ __volatile__("sync");
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}
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enable_interrupts();
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return 0;
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}
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}
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return cmd_usage(cmdtp);
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}
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U_BOOT_CMD(ecc, 4, 0, do_ecc,
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"support for DDR ECC features",
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"status - print out status info\n"
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"ecc captureclear - clear capture regs data\n"
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"ecc sbecnt <val> - set Single-Bit Error counter\n"
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"ecc sbethr <val> - set Single-Bit Threshold\n"
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"ecc errdisable <flag> - clear/set disable Memory Error Disable, flag:\n"
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" [-|+]sbe - Single-Bit Error\n"
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" [-|+]mbe - Multiple-Bit Error\n"
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" [-|+]mse - Memory Select Error\n"
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" [-|+]all - all errors\n"
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"ecc errdetectclr <flag> - clear Memory Error Detect, flag:\n"
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" mme - Multiple Memory Errors\n"
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" sbe - Single-Bit Error\n"
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" mbe - Multiple-Bit Error\n"
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" mse - Memory Select Error\n"
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" all - all errors\n"
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"ecc injectdatahi <hi> - set Memory Data Path Error Injection Mask High\n"
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"ecc injectdatalo <lo> - set Memory Data Path Error Injection Mask Low\n"
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"ecc injectecc <ecc> - set ECC Error Injection Mask\n"
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"ecc inject <en|dis> - enable/disable error injection\n"
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"ecc mirror <en|dis> - enable/disable mirror byte\n"
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"ecc testdw <addr> <cnt> - test mem region with double word access:\n"
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" - enables injects\n"
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" - writes pattern injecting errors with double word access\n"
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" - disables injects\n"
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" - reads pattern back with double word access, generates error\n"
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" - re-inits memory\n"
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"ecc testword <addr> <cnt> - test mem region with word access:\n"
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" - enables injects\n"
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" - writes pattern injecting errors with word access\n"
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" - writes pattern with word access, generates error\n"
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" - disables injects\n" " - re-inits memory");
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#endif
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