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![Bin Meng](/assets/img/avatar_default.png)
This adds initial Intel Braswell SoC support. It uses Intel FSP to initialize the chipset. Similar to its predecessor BayTrail, there are some work to do to enable the legacy UART integrated in the Braswell SoC. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
171 lines
3.7 KiB
C
171 lines
3.7 KiB
C
/*
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* Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Derived from arch/x86/cpu/baytrail/cpu.c
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*/
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#include <common.h>
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#include <cpu.h>
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#include <dm.h>
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#include <asm/cpu.h>
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#include <asm/cpu_x86.h>
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#include <asm/io.h>
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#include <asm/lapic.h>
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#include <asm/msr.h>
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#include <asm/turbo.h>
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static const unsigned int braswell_bus_freq_table[] = {
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83333333,
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100000000,
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133333333,
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116666666,
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80000000,
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93333333,
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90000000,
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88900000,
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87500000
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};
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static unsigned int braswell_bus_freq(void)
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{
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msr_t clk_info = msr_read(MSR_BSEL_CR_OVERCLOCK_CONTROL);
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if ((clk_info.lo & 0xf) < (ARRAY_SIZE(braswell_bus_freq_table)))
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return braswell_bus_freq_table[clk_info.lo & 0xf];
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return 0;
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}
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static unsigned long braswell_tsc_freq(void)
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{
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msr_t platform_info;
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ulong bclk = braswell_bus_freq();
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if (!bclk)
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return 0;
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platform_info = msr_read(MSR_PLATFORM_INFO);
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return bclk * ((platform_info.lo >> 8) & 0xff);
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}
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static int braswell_get_info(struct udevice *dev, struct cpu_info *info)
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{
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info->cpu_freq = braswell_tsc_freq();
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info->features = (1 << CPU_FEAT_L1_CACHE) | (1 << CPU_FEAT_MMU);
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return 0;
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}
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static int braswell_get_count(struct udevice *dev)
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{
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int ecx = 0;
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/*
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* Use the algorithm described in Intel 64 and IA-32 Architectures
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* Software Developer's Manual Volume 3 (3A, 3B & 3C): System
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* Programming Guide, Jan-2015. Section 8.9.2: Hierarchical Mapping
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* of CPUID Extended Topology Leaf.
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*/
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while (1) {
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struct cpuid_result leaf_b;
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leaf_b = cpuid_ext(0xb, ecx);
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/*
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* Braswell doesn't have hyperthreading so just determine the
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* number of cores by from level type (ecx[15:8] == * 2)
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*/
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if ((leaf_b.ecx & 0xff00) == 0x0200)
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return leaf_b.ebx & 0xffff;
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ecx++;
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}
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return 0;
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}
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static void braswell_set_max_freq(void)
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{
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msr_t perf_ctl;
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msr_t msr;
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/* Enable speed step */
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msr = msr_read(MSR_IA32_MISC_ENABLES);
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msr.lo |= (1 << 16);
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msr_write(MSR_IA32_MISC_ENABLES, msr);
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/* Enable Burst Mode */
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msr = msr_read(MSR_IA32_MISC_ENABLES);
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msr.hi = 0;
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msr_write(MSR_IA32_MISC_ENABLES, msr);
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/*
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* Set guaranteed ratio [21:16] from IACORE_TURBO_RATIOS to
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* bits [15:8] of the PERF_CTL
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*/
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msr = msr_read(MSR_IACORE_TURBO_RATIOS);
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perf_ctl.lo = (msr.lo & 0x3f0000) >> 8;
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/*
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* Set guaranteed vid [22:16] from IACORE_TURBO_VIDS to
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* bits [7:0] of the PERF_CTL
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*/
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msr = msr_read(MSR_IACORE_TURBO_VIDS);
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perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16;
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perf_ctl.hi = 0;
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msr_write(MSR_IA32_PERF_CTL, perf_ctl);
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}
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static int braswell_probe(struct udevice *dev)
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{
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debug("Init Braswell core\n");
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/*
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* On Braswell the turbo disable bit is actually scoped at the
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* building-block level, not package. For non-BSP cores that are
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* within a building block, enable turbo. The cores within the BSP's
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* building block will just see it already enabled and move on.
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*/
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if (lapicid())
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turbo_enable();
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/* Dynamic L2 shrink enable and threshold, clear SINGLE_PCTL bit 11 */
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msr_clrsetbits_64(MSR_PMG_CST_CONFIG_CONTROL, 0x3f080f, 0xe0008),
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msr_clrsetbits_64(MSR_POWER_MISC,
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ENABLE_ULFM_AUTOCM_MASK | ENABLE_INDP_AUTOCM_MASK, 0);
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/* Disable C1E */
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msr_clrsetbits_64(MSR_POWER_CTL, 2, 0);
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msr_setbits_64(MSR_POWER_MISC, 0x44);
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/* Set this core to max frequency ratio */
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braswell_set_max_freq();
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return 0;
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}
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static const struct udevice_id braswell_ids[] = {
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{ .compatible = "intel,braswell-cpu" },
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{ }
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};
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static const struct cpu_ops braswell_ops = {
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.get_desc = cpu_x86_get_desc,
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.get_info = braswell_get_info,
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.get_count = braswell_get_count,
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.get_vendor = cpu_x86_get_vendor,
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};
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U_BOOT_DRIVER(cpu_x86_braswell_drv) = {
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.name = "cpu_x86_braswell",
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.id = UCLASS_CPU,
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.of_match = braswell_ids,
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.bind = cpu_x86_bind,
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.probe = braswell_probe,
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.ops = &braswell_ops,
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};
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