mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-27 05:13:44 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
192 lines
5.8 KiB
C
192 lines
5.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2000-2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <mpc8xx.h>
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#include <asm/cpm_8xx.h>
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#include <asm/io.h>
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/*
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* Breath some life into the CPU...
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*
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* Set up the memory map,
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* initialize a bunch of registers,
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* initialize the UPM's
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*/
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void cpu_init_f(immap_t __iomem *immr)
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{
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memctl8xx_t __iomem *memctl = &immr->im_memctl;
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ulong reg;
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/* SYPCR - contains watchdog control (11-9) */
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#ifndef CONFIG_HW_WATCHDOG
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/* deactivate watchdog if not enabled in config */
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out_be32(&immr->im_siu_conf.sc_sypcr, CONFIG_SYS_SYPCR & ~SYPCR_SWE);
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#endif
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WATCHDOG_RESET();
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/* SIUMCR - contains debug pin configuration (11-6) */
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setbits_be32(&immr->im_siu_conf.sc_siumcr, CONFIG_SYS_SIUMCR);
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/* initialize timebase status and control register (11-26) */
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/* unlock TBSCRK */
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out_be32(&immr->im_sitk.sitk_tbscrk, KAPWR_KEY);
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out_be16(&immr->im_sit.sit_tbscr, CONFIG_SYS_TBSCR | TBSCR_TBE);
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/* Unlock timebase register */
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out_be32(&immr->im_sitk.sitk_tbk, KAPWR_KEY);
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/* initialize the PIT (11-31) */
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out_be32(&immr->im_sitk.sitk_piscrk, KAPWR_KEY);
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out_be16(&immr->im_sit.sit_piscr, CONFIG_SYS_PISCR);
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/* System integration timers. Don't change EBDF! (15-27) */
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out_be32(&immr->im_clkrstk.cark_sccrk, KAPWR_KEY);
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clrsetbits_be32(&immr->im_clkrst.car_sccr, ~CONFIG_SYS_SCCR_MASK,
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CONFIG_SYS_SCCR);
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/*
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* MPC866/885 ERRATA GLL2
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* Description:
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* In 1:2:1 mode, when HRESET is detected at the positive edge of
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* EXTCLK, then there will be a loss of phase between
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* EXTCLK and CLKOUT.
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*
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* Workaround:
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* Reprogram the SCCR:
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* 1. Write 1'b00 to SCCR[EBDF].
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* 2. Write 1'b01 to SCCR[EBDF].
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* 3. Rewrite the desired value to the PLPRCR register.
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*/
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reg = in_be32(&immr->im_clkrst.car_sccr);
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/* Are we in mode 1:2:1 ? */
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if ((reg & SCCR_EBDF11) == SCCR_EBDF01) {
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clrbits_be32(&immr->im_clkrst.car_sccr, SCCR_EBDF11);
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setbits_be32(&immr->im_clkrst.car_sccr, SCCR_EBDF01);
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}
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/* PLL (CPU clock) settings (15-30) */
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out_be32(&immr->im_clkrstk.cark_plprcrk, KAPWR_KEY);
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/* If CONFIG_SYS_PLPRCR (set in the various *_config.h files) tries to
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* set the MF field, then just copy CONFIG_SYS_PLPRCR over car_plprcr,
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* otherwise OR in CONFIG_SYS_PLPRCR so we do not change the current MF
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* field value.
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*
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* For newer (starting MPC866) chips PLPRCR layout is different.
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*/
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#ifdef CONFIG_SYS_PLPRCR
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if ((CONFIG_SYS_PLPRCR & PLPRCR_MFACT_MSK) != 0) /* reset control bits*/
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out_be32(&immr->im_clkrst.car_plprcr, CONFIG_SYS_PLPRCR);
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else /* isolate MF-related fields and reset control bits */
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clrsetbits_be32(&immr->im_clkrst.car_plprcr, ~PLPRCR_MFACT_MSK,
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CONFIG_SYS_PLPRCR);
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#endif
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/*
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* Memory Controller:
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*/
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/* Clear everything except Port Size bits & add the "Bank Valid" bit */
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clrsetbits_be32(&memctl->memc_br0, ~BR_PS_MSK, BR_V);
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/* Map banks 0 (and maybe 1) to the FLASH banks 0 (and 1) at
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* preliminary addresses - these have to be modified later
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* when FLASH size has been determined
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*
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* Depending on the size of the memory region defined by
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* CONFIG_SYS_OR0_REMAP some boards (wide address mask) allow to map the
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* CONFIG_SYS_MONITOR_BASE, while others (narrower address mask) can't
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* map CONFIG_SYS_MONITOR_BASE.
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*
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* For example, for CONFIG_IVMS8, the CONFIG_SYS_MONITOR_BASE is
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* 0xff000000, but CONFIG_SYS_OR0_REMAP's address mask is 0xfff80000.
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*
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* If BR0 wasn't loaded with address base 0xff000000, then BR0's
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* base address remains as 0x00000000. However, the address mask
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* have been narrowed to 512Kb, so CONFIG_SYS_MONITOR_BASE wasn't mapped
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* into the Bank0.
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*
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* This is why CONFIG_IVMS8 and similar boards must load BR0 with
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* CONFIG_SYS_BR0_PRELIM in advance.
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*
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* [Thanks to Michael Liao for this explanation.
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* I owe him a free beer. - wd]
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*/
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#if defined(CONFIG_SYS_OR0_REMAP)
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out_be32(&memctl->memc_or0, CONFIG_SYS_OR0_REMAP);
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#endif
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#if defined(CONFIG_SYS_OR1_REMAP)
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out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_REMAP);
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#endif
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#if defined(CONFIG_SYS_OR5_REMAP)
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out_be32(&memctl->memc_or5, CONFIG_SYS_OR5_REMAP);
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#endif
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/* now restrict to preliminary range */
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out_be32(&memctl->memc_br0, CONFIG_SYS_BR0_PRELIM);
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out_be32(&memctl->memc_or0, CONFIG_SYS_OR0_PRELIM);
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#if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM))
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out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_PRELIM);
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out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_PRELIM);
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#endif
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#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
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out_be32(&memctl->memc_or2, CONFIG_SYS_OR2_PRELIM);
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out_be32(&memctl->memc_br2, CONFIG_SYS_BR2_PRELIM);
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#endif
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#if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
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out_be32(&memctl->memc_or3, CONFIG_SYS_OR3_PRELIM);
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out_be32(&memctl->memc_br3, CONFIG_SYS_BR3_PRELIM);
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#endif
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#if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM)
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out_be32(&memctl->memc_or4, CONFIG_SYS_OR4_PRELIM);
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out_be32(&memctl->memc_br4, CONFIG_SYS_BR4_PRELIM);
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#endif
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#if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM)
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out_be32(&memctl->memc_or5, CONFIG_SYS_OR5_PRELIM);
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out_be32(&memctl->memc_br5, CONFIG_SYS_BR5_PRELIM);
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#endif
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#if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM)
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out_be32(&memctl->memc_or6, CONFIG_SYS_OR6_PRELIM);
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out_be32(&memctl->memc_br6, CONFIG_SYS_BR6_PRELIM);
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#endif
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#if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM)
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out_be32(&memctl->memc_or7, CONFIG_SYS_OR7_PRELIM);
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out_be32(&memctl->memc_br7, CONFIG_SYS_BR7_PRELIM);
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#endif
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/*
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* Reset CPM
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*/
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out_be16(&immr->im_cpm.cp_cpcr, CPM_CR_RST | CPM_CR_FLG);
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/* Spin until command processed */
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while (in_be16(&immr->im_cpm.cp_cpcr) & CPM_CR_FLG)
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;
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}
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/*
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* initialize higher level parts of CPU like timers
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*/
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int cpu_init_r(void)
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{
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return 0;
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}
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