mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-27 05:13:44 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
129 lines
2.9 KiB
C
129 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2008-2010 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <ioports.h>
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#include <lmb.h>
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#include <asm/io.h>
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#include <asm/mp.h>
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DECLARE_GLOBAL_DATA_PTR;
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int cpu_reset(int nr)
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{
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/* dummy function so common/cmd_mp.c will build
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* should be implemented in the future, when cpu_release()
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* is supported. Be aware there may be a similiar bug
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* as exists on MPC85xx w/its PIC having a timing window
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* associated to resetting the core */
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return 1;
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}
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int cpu_status(int nr)
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{
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/* dummy function so common/cmd_mp.c will build */
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return 0;
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}
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int cpu_disable(int nr)
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{
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
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volatile ccsr_gur_t *gur = &immap->im_gur;
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switch (nr) {
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case 0:
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setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_CPU0);
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break;
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case 1:
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setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_CPU1);
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break;
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default:
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printf("Invalid cpu number for disable %d\n", nr);
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return 1;
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}
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return 0;
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}
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int is_core_disabled(int nr) {
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immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
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ccsr_gur_t *gur = &immap->im_gur;
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u32 devdisr = in_be32(&gur->devdisr);
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switch (nr) {
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case 0:
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return (devdisr & MPC86xx_DEVDISR_CPU0);
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case 1:
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return (devdisr & MPC86xx_DEVDISR_CPU1);
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default:
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printf("Invalid cpu number for disable %d\n", nr);
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}
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return 0;
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}
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int cpu_release(int nr, int argc, char * const argv[])
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{
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/* dummy function so common/cmd_mp.c will build
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* should be implemented in the future */
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return 1;
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}
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u32 determine_mp_bootpg(unsigned int *pagesize)
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{
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if (pagesize)
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*pagesize = 4096;
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/* if we have 4G or more of memory, put the boot page at 4Gb-1M */
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if ((u64)gd->ram_size > 0xfffff000)
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return (0xfff00000);
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return (gd->ram_size - (1024 * 1024));
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}
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void cpu_mp_lmb_reserve(struct lmb *lmb)
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{
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u32 bootpg = determine_mp_bootpg(NULL);
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/* tell u-boot we stole a page */
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lmb_reserve(lmb, bootpg, 4096);
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}
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/*
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* Copy the code for other cpus to execute into an
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* aligned location accessible via BPTR
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*/
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void setup_mp(void)
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{
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extern ulong __secondary_start_page;
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ulong fixup = (ulong)&__secondary_start_page;
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u32 bootpg = determine_mp_bootpg(NULL);
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u32 bootpg_va;
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if (bootpg >= CONFIG_SYS_MAX_DDR_BAT_SIZE) {
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/* We're not covered by the DDR mapping, set up BAT */
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write_bat(DBAT7, CONFIG_SYS_SCRATCH_VA | BATU_BL_128K |
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BATU_VS | BATU_VP,
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bootpg | BATL_PP_RW | BATL_MEMCOHERENCE);
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bootpg_va = CONFIG_SYS_SCRATCH_VA;
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} else {
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bootpg_va = bootpg;
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}
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memcpy((void *)bootpg_va, (void *)fixup, 4096);
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flush_cache(bootpg_va, 4096);
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/* remove the temporary BAT mapping */
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if (bootpg >= CONFIG_SYS_MAX_DDR_BAT_SIZE)
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write_bat(DBAT7, 0, 0);
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/* If the physical location of bootpg is not at fff00000, set BPTR */
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if (bootpg != 0xfff00000)
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out_be32((uint *)(CONFIG_SYS_CCSRBAR + 0x20), 0x80000000 |
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(bootpg >> 12));
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}
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