mirror of
https://github.com/brain-hackers/u-boot-brain
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5411988242
This board uses the same CPU (8309) as VECT1. The memory however is different since it has NAND Flash, the NOR Flash partitioning is different and of course the FPGAs as well. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Signed-off-by: Christoph Dietrich <christoph.dietrich@keymile.com>
205 lines
6.2 KiB
C
205 lines
6.2 KiB
C
/*
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* Copyright (C) 2006 Freescale Semiconductor, Inc.
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* Dave Liu <daveliu@freescale.com>
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*
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* Copyright (C) 2007 Logic Product Development, Inc.
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* Peter Barada <peterb@logicpd.com>
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*
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* Copyright (C) 2007 MontaVista Software, Inc.
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* Anton Vorontsov <avorontsov@ru.mvista.com>
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*
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* (C) Copyright 2010
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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*/
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/* This needs to be set prior to including km/km83xx-common.h */
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#define CONFIG_SYS_TEXT_BASE 0xF0000000
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#if defined(CONFIG_SUVD3) /* SUVD3 board specific */
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#define CONFIG_HOSTNAME suvd3
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#define CONFIG_KM_BOARD_NAME "suvd3"
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/* include common defines/options for all 8321 Keymile boards */
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#include "km/km8321-common.h"
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#elif defined(CONFIG_KMVECT1) /* VECT1 board specific */
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#define CONFIG_HOSTNAME kmvect1
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#define CONFIG_KM_BOARD_NAME "kmvect1"
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/* at end of uboot partition, before env */
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#define CONFIG_SYS_QE_FW_ADDR 0xF00B0000
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/* include common defines/options for all 8309 Keymile boards */
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#include "km/km8309-common.h"
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#elif defined(CONFIG_KMTEGR1) /* TEGR1 board specific */
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#define CONFIG_HOSTNAME kmtegr1
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#define CONFIG_KM_BOARD_NAME "kmtegr1"
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#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0"
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#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1"
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#define MTDIDS_DEFAULT "nor0=boot,nand0=app"
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#define MTDPARTS_DEFAULT "mtdparts=" \
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"boot:" \
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"768k(u-boot)," \
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"256k(qe-fw)," \
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"128k(env)," \
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"128k(envred)," \
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"-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");" \
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"app:" \
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"-(" CONFIG_KM_UBI_PARTITION_NAME_APP ");"
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#define CONFIG_ENV_ADDR 0xF0100000
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#define CONFIG_ENV_OFFSET 0x100000
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#define CONFIG_CMD_NAND
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#define CONFIG_NAND_ECC_BCH
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#define CONFIG_BCH
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#define CONFIG_NAND_KMETER1
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define NAND_MAX_CHIPS 1
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/* include common defines/options for all 8309 Keymile boards */
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#include "km/km8309-common.h"
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/* must be after the include because KMBEC_FPGA is otherwise undefined */
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#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
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#else
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#error Supported boards are: SUVD3, KMVECT1, KMTEGR1
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#endif
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#define CONFIG_SYS_APP1_BASE 0xA0000000
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#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */
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#define CONFIG_SYS_APP2_BASE 0xB0000000
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#define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */
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/* EEprom support */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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/*
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* Init Local Bus Memory Controller:
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*
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* Bank Bus Machine PortSz Size Device
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* ---- --- ------- ------ ----- ------
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* 2 Local UPMA 16 bit 256MB APP1
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* 3 Local GPCM 16 bit 256MB APP2
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*
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*/
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#if defined(CONFIG_SUVD3) || defined(CONFIG_KMVECT1)
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/*
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* APP1 on the local bus CS2
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*/
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#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE
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#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
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#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \
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BR_PS_16 | \
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BR_MS_UPMA | \
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BR_V)
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#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE))
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#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \
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BR_PS_16 | \
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BR_V)
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#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
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OR_GPCM_CSNT | \
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OR_GPCM_ACS_DIV4 | \
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OR_GPCM_SCY_3 | \
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OR_GPCM_TRLX_SET)
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#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \
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0x0000c000 | \
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MxMR_WLFx_2X)
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#elif defined(CONFIG_KMTEGR1)
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#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \
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BR_PS_16 | \
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BR_MS_GPCM | \
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BR_V)
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#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
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OR_GPCM_SCY_5 | \
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OR_GPCM_TRLX_CLEAR | \
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OR_GPCM_EHTR_CLEAR)
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#endif /* CONFIG_KMTEGR1 */
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#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE
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#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
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/*
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* MMU Setup
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*/
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#if defined(CONFIG_SUVD3) || defined(CONFIG_KMVECT1)
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/* APP1: icache cacheable, but dcache-inhibit and guarded */
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#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \
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BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | BATU_BL_256M | \
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BATU_VS | BATU_VP)
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#define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \
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BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
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#elif defined(CONFIG_KMTEGR1)
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#define CONFIG_SYS_IBAT5L (0)
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#define CONFIG_SYS_IBAT5U (0)
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#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
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#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
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#endif /* CONFIG_KMTEGR1 */
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#define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \
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BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | BATU_BL_256M | \
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BATU_VS | BATU_VP)
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#define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \
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BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
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/*
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* QE UEC ethernet configuration
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*/
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#if defined(CONFIG_KMVECT1)
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#define CONFIG_MV88E6352_SWITCH
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#define CONFIG_KM_MVEXTSW_ADDR 0x10
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/* ethernet port connected to simple switch 88e6122 (UEC0) */
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#define CONFIG_UEC_ETH1
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#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
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#define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
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#define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
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#define CONFIG_FIXED_PHY 0xFFFFFFFF
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#define CONFIG_SYS_FIXED_PHY_ADDR 0x1E /* unused address */
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#define CONFIG_SYS_FIXED_PHY_PORT(devnum, speed, duplex) \
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{devnum, speed, duplex}
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#define CONFIG_SYS_FIXED_PHY_PORTS \
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CONFIG_SYS_FIXED_PHY_PORT("UEC0", SPEED_100, DUPLEX_FULL)
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#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
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#define CONFIG_SYS_UEC1_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR
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#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
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#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
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#endif /* CONFIG_KMVECT1 */
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#if defined(CONFIG_KMVECT1) || defined(CONFIG_KMTEGR1)
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/* ethernet port connected to piggy (UEC2) */
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#define CONFIG_HAS_ETH1
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#define CONFIG_UEC_ETH2
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#define CONFIG_SYS_UEC2_UCC_NUM 2 /* UCC3 */
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#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
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#define CONFIG_SYS_UEC2_TX_CLK QE_CLK12
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#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
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#define CONFIG_SYS_UEC2_PHY_ADDR 0
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#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
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#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
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#endif /* CONFIG_KMVECT1 || CONFIG_KMTEGR1 */
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#endif /* __CONFIG_H */
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