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https://github.com/brain-hackers/u-boot-brain
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94172c7961
Convert clock manager for Gen5, Arria 10 and Stratix 10 from struct to defines. Change to get clock manager base address from DT node instead of using #define. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
190 lines
5.7 KiB
C
190 lines
5.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
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*
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*/
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#ifndef _CLOCK_MANAGER_S10_
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#define _CLOCK_MANAGER_S10_
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/* Clock speed accessors */
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unsigned long cm_get_mpu_clk_hz(void);
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unsigned long cm_get_sdram_clk_hz(void);
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unsigned int cm_get_l4_sp_clk_hz(void);
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unsigned int cm_get_mmc_controller_clk_hz(void);
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unsigned int cm_get_qspi_controller_clk_hz(void);
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unsigned int cm_get_spi_controller_clk_hz(void);
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const unsigned int cm_get_osc_clk_hz(void);
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const unsigned int cm_get_f2s_per_ref_clk_hz(void);
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const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
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const unsigned int cm_get_intosc_clk_hz(void);
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const unsigned int cm_get_fpga_clk_hz(void);
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#define CLKMGR_EOSC1_HZ 25000000
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#define CLKMGR_INTOSC_HZ 460000000
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#define CLKMGR_FPGA_CLK_HZ 50000000
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/* Clock configuration accessors */
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const struct cm_config * const cm_get_default_config(void);
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struct cm_config {
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/* main group */
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u32 main_pll_mpuclk;
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u32 main_pll_nocclk;
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u32 main_pll_cntr2clk;
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u32 main_pll_cntr3clk;
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u32 main_pll_cntr4clk;
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u32 main_pll_cntr5clk;
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u32 main_pll_cntr6clk;
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u32 main_pll_cntr7clk;
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u32 main_pll_cntr8clk;
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u32 main_pll_cntr9clk;
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u32 main_pll_nocdiv;
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u32 main_pll_pllglob;
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u32 main_pll_fdbck;
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u32 main_pll_pllc0;
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u32 main_pll_pllc1;
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u32 spare;
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/* peripheral group */
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u32 per_pll_cntr2clk;
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u32 per_pll_cntr3clk;
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u32 per_pll_cntr4clk;
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u32 per_pll_cntr5clk;
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u32 per_pll_cntr6clk;
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u32 per_pll_cntr7clk;
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u32 per_pll_cntr8clk;
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u32 per_pll_cntr9clk;
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u32 per_pll_emacctl;
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u32 per_pll_gpiodiv;
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u32 per_pll_pllglob;
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u32 per_pll_fdbck;
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u32 per_pll_pllc0;
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u32 per_pll_pllc1;
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/* incoming clock */
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u32 hps_osc_clk_hz;
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u32 fpga_clk_hz;
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};
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void cm_basic_init(const struct cm_config * const cfg);
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/* Control status */
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#define CLKMGR_S10_CTRL 0x00
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#define CLKMGR_S10_STAT 0x04
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#define CLKMGR_S10_INTRCLR 0x14
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/* Mainpll group */
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#define CLKMGR_S10_MAINPLL_EN 0x30
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#define CLKMGR_S10_MAINPLL_BYPASS 0x3c
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#define CLKMGR_S10_MAINPLL_MPUCLK 0x48
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#define CLKMGR_S10_MAINPLL_NOCCLK 0x4c
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#define CLKMGR_S10_MAINPLL_CNTR2CLK 0x50
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#define CLKMGR_S10_MAINPLL_CNTR3CLK 0x54
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#define CLKMGR_S10_MAINPLL_CNTR4CLK 0x58
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#define CLKMGR_S10_MAINPLL_CNTR5CLK 0x5c
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#define CLKMGR_S10_MAINPLL_CNTR6CLK 0x60
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#define CLKMGR_S10_MAINPLL_CNTR7CLK 0x64
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#define CLKMGR_S10_MAINPLL_CNTR8CLK 0x68
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#define CLKMGR_S10_MAINPLL_CNTR9CLK 0x6c
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#define CLKMGR_S10_MAINPLL_NOCDIV 0x70
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#define CLKMGR_S10_MAINPLL_PLLGLOB 0x74
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#define CLKMGR_S10_MAINPLL_FDBCK 0x78
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#define CLKMGR_S10_MAINPLL_MEMSTAT 0x80
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#define CLKMGR_S10_MAINPLL_PLLC0 0x84
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#define CLKMGR_S10_MAINPLL_PLLC1 0x88
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#define CLKMGR_S10_MAINPLL_VCOCALIB 0x8c
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/* Periphpll group */
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#define CLKMGR_S10_PERPLL_EN 0xa4
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#define CLKMGR_S10_PERPLL_BYPASS 0xac
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#define CLKMGR_S10_PERPLL_CNTR2CLK 0xbc
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#define CLKMGR_S10_PERPLL_CNTR3CLK 0xc0
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#define CLKMGR_S10_PERPLL_CNTR4CLK 0xc4
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#define CLKMGR_S10_PERPLL_CNTR5CLK 0xc8
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#define CLKMGR_S10_PERPLL_CNTR6CLK 0xcc
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#define CLKMGR_S10_PERPLL_CNTR7CLK 0xd0
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#define CLKMGR_S10_PERPLL_CNTR8CLK 0xd4
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#define CLKMGR_S10_PERPLL_CNTR9CLK 0xd8
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#define CLKMGR_S10_PERPLL_EMACCTL 0xdc
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#define CLKMGR_S10_PERPLL_GPIODIV 0xe0
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#define CLKMGR_S10_PERPLL_PLLGLOB 0xe4
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#define CLKMGR_S10_PERPLL_FDBCK 0xe8
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#define CLKMGR_S10_PERPLL_MEMSTAT 0xf0
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#define CLKMGR_S10_PERPLL_PLLC0 0xf4
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#define CLKMGR_S10_PERPLL_PLLC1 0xf8
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#define CLKMGR_S10_PERPLL_VCOCALIB 0xfc
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#define CLKMGR_STAT CLKMGR_S10_STAT
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#define CLKMGR_INTER CLKMGR_S10_INTER
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#define CLKMGR_PERPLL_EN CLKMGR_S10_PERPLL_EN
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#define CLKMGR_CTRL_SAFEMODE BIT(0)
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#define CLKMGR_BYPASS_MAINPLL_ALL 0x00000007
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#define CLKMGR_BYPASS_PERPLL_ALL 0x0000007f
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#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000001
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#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000002
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#define CLKMGR_INTER_MAINPLLLOST_MASK 0x00000004
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#define CLKMGR_INTER_PERPLLLOST_MASK 0x00000008
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#define CLKMGR_STAT_BUSY BIT(0)
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#define CLKMGR_STAT_MAINPLL_LOCKED BIT(8)
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#define CLKMGR_STAT_PERPLL_LOCKED BIT(9)
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#define CLKMGR_PLLGLOB_PD_MASK 0x00000001
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#define CLKMGR_PLLGLOB_RST_MASK 0x00000002
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#define CLKMGR_PLLGLOB_VCO_PSRC_MASK 0X3
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#define CLKMGR_PLLGLOB_VCO_PSRC_OFFSET 16
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#define CLKMGR_VCO_PSRC_EOSC1 0
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#define CLKMGR_VCO_PSRC_INTOSC 1
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#define CLKMGR_VCO_PSRC_F2S 2
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#define CLKMGR_PLLGLOB_REFCLKDIV_MASK 0X3f
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#define CLKMGR_PLLGLOB_REFCLKDIV_OFFSET 8
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#define CLKMGR_CLKSRC_MASK 0x7
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#define CLKMGR_CLKSRC_OFFSET 16
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#define CLKMGR_CLKSRC_MAIN 0
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#define CLKMGR_CLKSRC_PER 1
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#define CLKMGR_CLKSRC_OSC1 2
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#define CLKMGR_CLKSRC_INTOSC 3
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#define CLKMGR_CLKSRC_FPGA 4
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#define CLKMGR_CLKCNT_MSK 0x7ff
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#define CLKMGR_FDBCK_MDIV_MASK 0xff
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#define CLKMGR_FDBCK_MDIV_OFFSET 24
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#define CLKMGR_PLLC0_DIV_MASK 0xff
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#define CLKMGR_PLLC1_DIV_MASK 0xff
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#define CLKMGR_PLLC0_EN_OFFSET 27
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#define CLKMGR_PLLC1_EN_OFFSET 24
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#define CLKMGR_NOCDIV_L4MAIN_OFFSET 0
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#define CLKMGR_NOCDIV_L4MPCLK_OFFSET 8
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#define CLKMGR_NOCDIV_L4SPCLK_OFFSET 16
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#define CLKMGR_NOCDIV_CSATCLK_OFFSET 24
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#define CLKMGR_NOCDIV_CSTRACECLK_OFFSET 26
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#define CLKMGR_NOCDIV_CSPDBGCLK_OFFSET 28
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#define CLKMGR_NOCDIV_L4SPCLK_MASK 0X3
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#define CLKMGR_NOCDIV_DIV1 0
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#define CLKMGR_NOCDIV_DIV2 1
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#define CLKMGR_NOCDIV_DIV4 2
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#define CLKMGR_NOCDIV_DIV8 3
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#define CLKMGR_CSPDBGCLK_DIV1 0
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#define CLKMGR_CSPDBGCLK_DIV4 1
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#define CLKMGR_MSCNT_CONST 200
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#define CLKMGR_MDIV_CONST 6
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#define CLKMGR_HSCNT_CONST 9
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#define CLKMGR_VCOCALIB_MSCNT_MASK 0xff
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#define CLKMGR_VCOCALIB_MSCNT_OFFSET 9
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#define CLKMGR_VCOCALIB_HSCNT_MASK 0xff
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#define CLKMGR_EMACCTL_EMAC0SEL_OFFSET 26
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#define CLKMGR_EMACCTL_EMAC1SEL_OFFSET 27
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#define CLKMGR_EMACCTL_EMAC2SEL_OFFSET 28
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#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK 0x00000020
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#endif /* _CLOCK_MANAGER_S10_ */
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