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430b42f76a
commitc5de2b7eae("arm: socfpga: implement proper peripheral reset") has removed the call to 'reset_deassert_peripherals_handoff()' from socfpga gen5 SPL since the reset driver now handles resets. However, commitc1d4b464c8("ARM: socfpga: Disable bridges in SPL unless booting from FPGA") has re-added this ad-hoc reset code, so that all peripherals were now again enabled instead of letting the drivers enable them by request. While at it, remove this function for gen5 as it should not be used. Fixes: commitc1d4b464c8("ARM: socfpga: Disable bridges in SPL unless booting from FPGA") Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
50 lines
1.2 KiB
C
50 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
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*/
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#ifndef _RESET_MANAGER_GEN5_H_
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#define _RESET_MANAGER_GEN5_H_
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#include <dt-bindings/reset/altr,rst-mgr.h>
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void socfpga_bridges_set_handoff_regs(bool h2f, bool lwh2f, bool f2h);
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void socfpga_bridges_reset(int enable);
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struct socfpga_reset_manager {
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u32 status;
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u32 ctrl;
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u32 counts;
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u32 padding1;
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u32 mpu_mod_reset;
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u32 per_mod_reset;
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u32 per2_mod_reset;
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u32 brg_mod_reset;
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u32 misc_mod_reset;
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u32 padding2[12];
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u32 tstscratch;
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};
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/*
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* SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows:
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* 0 ... mpumodrst
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* 1 ... permodrst
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* 2 ... per2modrst
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* 3 ... brgmodrst
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* 4 ... miscmodrst
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*/
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#define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0)
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#define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1)
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#define RSTMGR_NAND RSTMGR_DEFINE(1, 4)
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#define RSTMGR_QSPI RSTMGR_DEFINE(1, 5)
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#define RSTMGR_L4WD0 RSTMGR_DEFINE(1, 6)
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#define RSTMGR_OSC1TIMER0 RSTMGR_DEFINE(1, 8)
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#define RSTMGR_UART0 RSTMGR_DEFINE(1, 16)
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#define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 18)
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#define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 19)
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#define RSTMGR_SDMMC RSTMGR_DEFINE(1, 22)
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#define RSTMGR_DMA RSTMGR_DEFINE(1, 28)
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#define RSTMGR_SDR RSTMGR_DEFINE(1, 29)
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#endif /* _RESET_MANAGER_GEN5_H_ */
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