mirror of
https://github.com/brain-hackers/u-boot-brain
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58e5e9aff1
The main purpose of this rewrite it to be able to share the same initialization code on all FSL PowerPC products that have DDR controllers. (83xx, 85xx, 86xx). The code is broken up into the following steps: GET_SPD COMPUTE_DIMM_PARMS COMPUTE_COMMON_PARMS GATHER_OPTS ASSIGN_ADDRESSES COMPUTE_REGS PROGRAM_REGS This allows us to share more code an easily allow for board specific code overrides. Additionally this code base adds support for >4G of DDR and provides a foundation for supporting interleaving on processors with more than one controller. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Becky Bruce <becky.bruce@freescale.com> Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
54 lines
1.6 KiB
C
54 lines
1.6 KiB
C
/*
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* Copyright 2008 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 as published by the Free Software Foundation.
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*/
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#ifndef COMMON_TIMING_PARAMS_H
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#define COMMON_TIMING_PARAMS_H
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typedef struct {
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/* parameters to constrict */
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unsigned int tCKmin_X_ps;
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unsigned int tCKmax_ps;
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unsigned int tCKmax_max_ps;
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unsigned int tRCD_ps;
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unsigned int tRP_ps;
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unsigned int tRAS_ps;
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unsigned int tWR_ps; /* maximum = 63750 ps */
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unsigned int tWTR_ps; /* maximum = 63750 ps */
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unsigned int tRFC_ps; /* maximum = 255 ns + 256 ns + .75 ns
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= 511750 ps */
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unsigned int tRRD_ps; /* maximum = 63750 ps */
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unsigned int tRC_ps; /* maximum = 254 ns + .75 ns = 254750 ps */
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unsigned int refresh_rate_ps;
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unsigned int tIS_ps; /* byte 32, spd->ca_setup */
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unsigned int tIH_ps; /* byte 33, spd->ca_hold */
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unsigned int tDS_ps; /* byte 34, spd->data_setup */
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unsigned int tDH_ps; /* byte 35, spd->data_hold */
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unsigned int tRTP_ps; /* byte 38, spd->trtp */
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unsigned int tDQSQ_max_ps; /* byte 44, spd->tdqsq */
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unsigned int tQHS_ps; /* byte 45, spd->tqhs */
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unsigned int ndimms_present;
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unsigned int lowest_common_SPD_caslat;
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unsigned int highest_common_derated_caslat;
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unsigned int additive_latency;
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unsigned int all_DIMMs_burst_lengths_bitmask;
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unsigned int all_DIMMs_registered;
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unsigned int all_DIMMs_unbuffered;
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unsigned int all_DIMMs_ECC_capable;
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unsigned long long total_mem;
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unsigned long long base_address;
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} common_timing_params_t;
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#endif
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