mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-10 05:06:16 +09:00
58e5e9aff1
The main purpose of this rewrite it to be able to share the same initialization code on all FSL PowerPC products that have DDR controllers. (83xx, 85xx, 86xx). The code is broken up into the following steps: GET_SPD COMPUTE_DIMM_PARMS COMPUTE_COMMON_PARMS GATHER_OPTS ASSIGN_ADDRESSES COMPUTE_REGS PROGRAM_REGS This allows us to share more code an easily allow for board specific code overrides. Additionally this code base adds support for >4G of DDR and provides a foundation for supporting interleaving on processors with more than one controller. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Becky Bruce <becky.bruce@freescale.com> Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
32 lines
812 B
Makefile
32 lines
812 B
Makefile
#
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# Copyright 2008 Freescale Semiconductor, Inc.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License
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# Version 2 as published by the Free Software Foundation.
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)libddr.a
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COBJS-$(CONFIG_FSL_DDR1) += main.o util.o ctrl_regs.o options.o \
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lc_common_dimm_params.o
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COBJS-$(CONFIG_FSL_DDR1) += ddr1_dimm_params.o
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COBJS-$(CONFIG_FSL_DDR2) += main.o util.o ctrl_regs.o options.o \
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lc_common_dimm_params.o
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COBJS-$(CONFIG_FSL_DDR2) += ddr2_dimm_params.o
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SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
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all: $(obj).depend $(LIB)
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$(LIB): $(OBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS)
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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