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This patch adds support for the QSPI IP found in stm32f7 devices. Signed-off-by: Michael Kurz <michi.kurz@gmail.com>
52 lines
1.2 KiB
C
52 lines
1.2 KiB
C
/*
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* (C) Copyright 2016
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* Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _STM32_RCC_H
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#define _STM32_RCC_H
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/*
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* RCC AHB1ENR specific definitions
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*/
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#define RCC_AHB1ENR_GPIO_A_EN BIT(0)
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#define RCC_AHB1ENR_GPIO_B_EN BIT(1)
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#define RCC_AHB1ENR_GPIO_C_EN BIT(2)
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#define RCC_AHB1ENR_GPIO_D_EN BIT(3)
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#define RCC_AHB1ENR_GPIO_E_EN BIT(4)
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#define RCC_AHB1ENR_GPIO_F_EN BIT(5)
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#define RCC_AHB1ENR_GPIO_G_EN BIT(6)
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#define RCC_AHB1ENR_GPIO_H_EN BIT(7)
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#define RCC_AHB1ENR_GPIO_I_EN BIT(8)
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#define RCC_AHB1ENR_GPIO_J_EN BIT(9)
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#define RCC_AHB1ENR_GPIO_K_EN BIT(10)
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#define RCC_AHB1ENR_ETHMAC_EN BIT(25)
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#define RCC_AHB1ENR_ETHMAC_TX_EN BIT(26)
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#define RCC_AHB1ENR_ETHMAC_RX_EN BIT(27)
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#define RCC_AHB1ENR_ETHMAC_PTP_EN BIT(28)
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/*
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* RCC AHB3ENR specific definitions
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*/
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#define RCC_AHB3ENR_FMC_EN BIT(0)
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#define RCC_AHB3ENR_QSPI_EN BIT(1)
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/*
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* RCC APB1ENR specific definitions
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*/
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#define RCC_APB1ENR_TIM2EN BIT(0)
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#define RCC_APB1ENR_USART2EN BIT(17)
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#define RCC_APB1ENR_USART3EN BIT(18)
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#define RCC_APB1ENR_PWREN BIT(28)
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/*
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* RCC APB2ENR specific definitions
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*/
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#define RCC_APB2ENR_USART1EN BIT(4)
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#define RCC_APB2ENR_USART6EN BIT(5)
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#define RCC_APB2ENR_SYSCFGEN BIT(14)
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#endif
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