mirror of
https://github.com/brain-hackers/u-boot-brain
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9d47d1316d
When running usb dwc3 gadget driver, we meet random USB enumeration failure in fastboot. The root cause is a cache coherence issue. When it happens, the ctrl_req in gadget driver is allocated at 0xfe932f40, and the usb_composite_dev (cdev) is allocated at 0xfe932f60. So after we submit the setup request (cache flushed) to USB controller, any accessing to usb_composite_dev variable will cause the cache line refill, then when setup transfer is completed, reading the setup data in ctrl_req will gets old value from cache not from memory. The ctrl_req is allocated by API dma_alloc_coherent, but u-boot don't have cohernet memory. so it still needs cache maintain operations before/after HW accessing. Since the cache flush or invalidate bases on cache line, so when the allocated memory size is not cache line aligned, potentially it may meet such issue. This patch modifies the dma_alloc_coherent API to round the size to cache line aligned. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
37 lines
831 B
C
37 lines
831 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2007
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* Stelian Pop <stelian@popies.net>
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* Lead Tech Design <www.leadtechdesign.com>
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*/
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#ifndef __ASM_ARM_DMA_MAPPING_H
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#define __ASM_ARM_DMA_MAPPING_H
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#include <linux/dma-direction.h>
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#define dma_mapping_error(x, y) 0
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static inline void *dma_alloc_coherent(size_t len, unsigned long *handle)
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{
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*handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, ROUND(len, ARCH_DMA_MINALIGN));
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return (void *)*handle;
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}
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static inline void dma_free_coherent(void *addr)
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{
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free(addr);
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}
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static inline unsigned long dma_map_single(volatile void *vaddr, size_t len,
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enum dma_data_direction dir)
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{
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return (unsigned long)vaddr;
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}
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static inline void dma_unmap_single(volatile void *vaddr, size_t len,
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unsigned long paddr)
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{
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}
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#endif /* __ASM_ARM_DMA_MAPPING_H */
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