mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-12 06:06:15 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
55 lines
2.2 KiB
C
55 lines
2.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
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*/
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#ifndef _TEGRA30_GP_PADCTRL_H_
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#define _TEGRA30_GP_PADCTRL_H_
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#include <asm/arch-tegra/gp_padctrl.h>
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/* APB_MISC_GP and padctrl registers */
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struct apb_misc_gp_ctlr {
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u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */
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u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */
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u32 reserved0[22]; /* 0x08 - 0x5C: */
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u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */
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u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
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u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
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u32 aocfg2; /* 0x6c: APB_MISC_GP_AOCFG2PADCTRL */
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u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
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u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
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u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */
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u32 atcfg4; /* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */
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u32 atcfg5; /* 0x80: APB_MISC_GP_ATCFG5PADCTRL */
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u32 cdev1cfg; /* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */
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u32 cdev2cfg; /* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */
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u32 csuscfg; /* 0x8C: APB_MISC_GP_CSUSCFGPADCTRL */
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u32 dap1cfg; /* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */
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u32 dap2cfg; /* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */
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u32 dap3cfg; /* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */
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u32 dap4cfg; /* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */
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u32 dbgcfg; /* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */
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u32 lcdcfg1; /* 0xA4: APB_MISC_GP_LCDCFG1PADCTRL */
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u32 lcdcfg2; /* 0xA8: APB_MISC_GP_LCDCFG2PADCTRL */
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u32 sdio2cfg; /* 0xAC: APB_MISC_GP_SDIO2CFGPADCTRL */
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u32 sdio3cfg; /* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */
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u32 spicfg; /* 0xB4: APB_MISC_GP_SPICFGPADCTRL */
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u32 uaacfg; /* 0xB8: APB_MISC_GP_UAACFGPADCTRL */
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u32 uabcfg; /* 0xBC: APB_MISC_GP_UABCFGPADCTRL */
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u32 uart2cfg; /* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */
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u32 uart3cfg; /* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */
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u32 vicfg1; /* 0xC8: APB_MISC_GP_VICFG1PADCTRL */
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u32 vivttgen; /* 0xCC: APB_MISC_GP_VIVTTGENPADCTRL */
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u32 reserved1[7]; /* 0xD0-0xE8: */
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u32 sdio1cfg; /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */
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};
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/* SDMMC1/3 settings from section 24.6 of T30 TRM */
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#define SDIOCFG_DRVUP_SLWF 1
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#define SDIOCFG_DRVDN_SLWR 1
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#define SDIOCFG_DRVUP 0x2E
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#define SDIOCFG_DRVDN 0x2A
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#endif /* _TEGRA30_GP_PADCTRL_H_ */
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