mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-12 06:06:15 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
91 lines
3.8 KiB
C
91 lines
3.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2013-2015
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* NVIDIA Corporation <www.nvidia.com>
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*/
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#ifndef _TEGRA210_AHB_H_
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#define _TEGRA210_AHB_H_
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struct ahb_ctlr {
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u32 reserved0; /* 00h */
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u32 arbitration_disable; /* _ARBITRATION_DISABLE_0, 04h */
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u32 arbitration_priority_ctrl; /* _ARBITRATION_PRIORITY_CTRL_0,08h */
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u32 arbitration_usr_protect; /* _ARBITRATION_USR_PROTECT_0, 0ch */
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u32 gizmo_ahb_mem; /* _GIZMO_AHB_MEM_0, 10h */
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u32 gizmo_apb_dma; /* _GIZMO_APB_DMA_0, 14h */
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u32 reserved6[2]; /* 18h, 1ch */
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u32 gizmo_usb; /* _GIZMO_USB_0, 20h */
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u32 gizmo_ahb_xbar_bridge; /* _GIZMO_AHB_XBAR_BRIDGE_0, 24h */
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u32 gizmo_cpu_ahb_bridge; /* _GIZMO_CPU_AHB_BRIDGE_0, 28h */
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u32 gizmo_cop_ahb_bridge; /* _GIZMO_COP_AHB_BRIDGE_0, 2ch */
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u32 gizmo_xbar_apb_ctlr; /* _GIZMO_XBAR_APB_CTLR_0, 30h */
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u32 gizmo_vcp_ahb_bridge; /* _GIZMO_VCP_AHB_BRIDGE_0, 34h */
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u32 reserved13[2]; /* 38h, 3ch */
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u32 gizmo_nand; /* _GIZMO_NAND_0, 40h */
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u32 reserved15; /* 44h */
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u32 gizmo_sdmmc4; /* _GIZMO_SDMMC4_0, 48h */
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u32 reserved17; /* 4ch */
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u32 gizmo_se; /* _GIZMO_SE_0, 50h */
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u32 gizmo_tzram; /* _GIZMO_TZRAM_0, 54h */
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u32 reserved20[3]; /* 58h, 5ch, 60h */
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u32 gizmo_bsev; /* _GIZMO_BSEV_0, 64h */
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u32 reserved22[3]; /* 68h, 6ch, 70h */
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u32 gizmo_bsea; /* _GIZMO_BSEA_0, 74h */
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u32 gizmo_nor; /* _GIZMO_NOR_0, 78h */
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u32 gizmo_usb2; /* _GIZMO_USB2_0, 7ch */
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u32 gizmo_usb3; /* _GIZMO_USB3_0, 80h */
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u32 gizmo_sdmmc1; /* _GIZMO_SDMMC1_0, 84h */
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u32 gizmo_sdmmc2; /* _GIZMO_SDMMC2_0, 88h */
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u32 gizmo_sdmmc3; /* _GIZMO_SDMMC3_0, 8ch */
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u32 reserved30[13]; /* 90h ~ c0h */
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u32 ahb_wrq_empty; /* _AHB_WRQ_EMPTY_0, c4h */
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u32 reserved32[5]; /* c8h ~ d8h */
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u32 ahb_mem_prefetch_cfg_x; /* _AHB_MEM_PREFETCH_CFG_X_0, dch */
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u32 arbitration_xbar_ctrl; /* _ARBITRATION_XBAR_CTRL_0, e0h */
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u32 ahb_mem_prefetch_cfg3; /* _AHB_MEM_PREFETCH_CFG3_0, e4h */
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u32 ahb_mem_prefetch_cfg4; /* _AHB_MEM_PREFETCH_CFG3_0, e8h */
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u32 avp_ppcs_rd_coh_status; /* _AVP_PPCS_RD_COH_STATUS_0, ech */
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u32 ahb_mem_prefetch_cfg1; /* _AHB_MEM_PREFETCH_CFG1_0, f0h */
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u32 ahb_mem_prefetch_cfg2; /* _AHB_MEM_PREFETCH_CFG2_0, f4h */
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u32 ahbslvmem_status; /* _AHBSLVMEM_STATUS_0, f8h */
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/* _ARBITRATION_AHB_MEM_WRQUE_MST_ID_0, fch */
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u32 arbitration_ahb_mem_wrque_mst_id;
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u32 arbitration_cpu_abort_addr; /* _ARBITRATION_CPU_ABORT_ADDR_0,100h */
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u32 arbitration_cpu_abort_info; /* _ARBITRATION_CPU_ABORT_INFO_0,104h */
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u32 arbitration_cop_abort_addr; /* _ARBITRATION_COP_ABORT_ADDR_0,108h */
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u32 arbitration_cop_abort_info; /* _ARBITRATION_COP_ABORT_INFO_0,10ch */
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u32 reserved46[4]; /* 110h ~ 11ch */
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u32 avpc_mccif_fifoctrl; /* _AVPC_MCCIF_FIFOCTRL_0, 120h */
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u32 timeout_wcoal_avpc; /* _TIMEOUT_WCOAL_AVPC_0, 124h */
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u32 mpcorelp_mccif_fifoctrl; /* _MPCORELP_MCCIF_FIFOCTRL_0, 128h */
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u32 mpcore_mccif_fifoctrl; /* _MPCORE_MCCIF_FIFOCTRL_0, 12ch */
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u32 axicif_fastsync_ctrl; /* AXICIF_FASTSYNC_CTRL_0, 130h */
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u32 axicif_fastsync_statistics; /* _AXICIF_FASTSYNC_STATISTICS_0,134h */
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/* _AXICIF_FASTSYNC0_CPUCLK_TO_MCCLK_0, 138h */
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u32 axicif_fastsync0_cpuclk_to_mcclk;
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/* _AXICIF_FASTSYNC1_CPUCLK_TO_MCCLK_0, 13ch */
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u32 axicif_fastsync1_cpuclk_to_mcclk;
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/* _AXICIF_FASTSYNC2_CPUCLK_TO_MCCLK_0, 140h */
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u32 axicif_fastsync2_cpuclk_to_mcclk;
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/* _AXICIF_FASTSYNC0_MCCLK_TO_CPUCLK_0, 144h */
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u32 axicif_fastsync0_mcclk_to_cpuclk;
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/* _AXICIF_FASTSYNC1_MCCLK_TO_CPUCLK_0, 148h */
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u32 axicif_fastsync1_mcclk_to_cpuclk;
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/* _AXICIF_FASTSYNC2_MCCLK_TO_CPUCLK_0, 14ch */
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u32 axicif_fastsync2_mcclk_to_cpuclk;
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};
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#define PPSB_STOPCLK_ENABLE (1 << 2)
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#define GIZ_ENABLE_SPLIT (1 << 0)
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#define GIZ_ENB_FAST_REARB (1 << 2)
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#define GIZ_DONT_SPLIT_AHB_WR (1 << 7)
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#define GIZ_USB_IMMEDIATE (1 << 18)
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/* AHB_ARBITRATION_XBAR_CTRL_0 0xe0 */
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#define ARBITRATION_XBAR_CTRL_PPSB_ENABLE (1 << 2)
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#endif /* _TEGRA210_AHB_H_ */
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