mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-12 06:06:15 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
69 lines
2.2 KiB
C
69 lines
2.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
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* Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
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*/
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#ifndef __STI_SDHCI_H__
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#define __STI_SDHCI_H__
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#define FLASHSS_MMC_CORE_CONFIG_1 0x400
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#define FLASHSS_MMC_CORECFG_TIMEOUT_CLK_UNIT_MHZ BIT(24)
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#define FLASHSS_MMC_CORECFG_TIMEOUT_CLK_FREQ_MIN BIT(12)
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#define STI_FLASHSS_MMC_CORE_CONFIG_1 \
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(FLASHSS_MMC_CORECFG_TIMEOUT_CLK_UNIT_MHZ | \
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FLASHSS_MMC_CORECFG_TIMEOUT_CLK_FREQ_MIN)
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#define FLASHSS_MMC_CORE_CONFIG_2 0x404
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#define FLASHSS_MMC_CORECFG_HIGH_SPEED BIT(28)
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#define FLASHSS_MMC_CORECFG_8BIT_EMMC BIT(20)
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#define MAX_BLK_LENGTH_1024 BIT(16)
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#define BASE_CLK_FREQ_200 0xc8
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#define STI_FLASHSS_MMC_CORE_CONFIG2 \
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(FLASHSS_MMC_CORECFG_HIGH_SPEED | \
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FLASHSS_MMC_CORECFG_8BIT_EMMC | \
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MAX_BLK_LENGTH_1024 | \
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BASE_CLK_FREQ_200 << 0)
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#define STI_FLASHSS_SDCARD_CORE_CONFIG2 \
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(FLASHSS_MMC_CORECFG_HIGH_SPEED | \
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MAX_BLK_LENGTH_1024 | \
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BASE_CLK_FREQ_200)
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#define FLASHSS_MMC_CORE_CONFIG_3 0x408
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#define FLASHSS_MMC_CORECFG_SLOT_TYPE_EMMC BIT(28)
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#define FLASHSS_MMC_CORECFG_ASYNCH_INTR_SUPPORT BIT(20)
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#define FLASHSS_MMC_CORECFG_3P3_VOLT BIT(8)
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#define FLASHSS_MMC_CORECFG_SUSP_RES_SUPPORT BIT(4)
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#define FLASHSS_MMC_CORECFG_SDMA BIT(0)
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#define STI_FLASHSS_MMC_CORE_CONFIG3 \
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(FLASHSS_MMC_CORECFG_SLOT_TYPE_EMMC | \
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FLASHSS_MMC_CORECFG_ASYNCH_INTR_SUPPORT | \
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FLASHSS_MMC_CORECFG_3P3_VOLT | \
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FLASHSS_MMC_CORECFG_SUSP_RES_SUPPORT | \
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FLASHSS_MMC_CORECFG_SDMA)
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#define STI_FLASHSS_SDCARD_CORE_CONFIG3 \
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(FLASHSS_MMC_CORECFG_ASYNCH_INTR_SUPPORT | \
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FLASHSS_MMC_CORECFG_3P3_VOLT | \
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FLASHSS_MMC_CORECFG_SUSP_RES_SUPPORT | \
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FLASHSS_MMC_CORECFG_SDMA)
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#define FLASHSS_MMC_CORE_CONFIG_4 0x40c
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#define FLASHSS_MMC_CORECFG_D_DRIVER_SUPPORT BIT(20)
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#define FLASHSS_MMC_CORECFG_C_DRIVER_SUPPORT BIT(16)
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#define FLASHSS_MMC_CORECFG_A_DRIVER_SUPPORT BIT(12)
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#define STI_FLASHSS_MMC_CORE_CONFIG4 \
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(FLASHSS_MMC_CORECFG_D_DRIVER_SUPPORT | \
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FLASHSS_MMC_CORECFG_C_DRIVER_SUPPORT | \
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FLASHSS_MMC_CORECFG_A_DRIVER_SUPPORT)
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#define ST_MMC_CCONFIG_REG_5 0x210
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#define SYSCONF_MMC1_ENABLE_BIT 3
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#endif /* _STI_SDHCI_H_ */
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