mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-12 06:06:15 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
245 lines
7.0 KiB
C
245 lines
7.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (c) 2016 Google, Inc
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*/
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#ifndef _ASM_ARCH_SCU_AST2500_H
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#define _ASM_ARCH_SCU_AST2500_H
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#define SCU_UNLOCK_VALUE 0x1688a8a8
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#define SCU_HWSTRAP_VGAMEM_SHIFT 2
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#define SCU_HWSTRAP_VGAMEM_MASK (3 << SCU_HWSTRAP_VGAMEM_SHIFT)
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#define SCU_HWSTRAP_MAC1_RGMII (1 << 6)
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#define SCU_HWSTRAP_MAC2_RGMII (1 << 7)
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#define SCU_HWSTRAP_DDR4 (1 << 24)
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#define SCU_HWSTRAP_CLKIN_25MHZ (1 << 23)
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#define SCU_MPLL_DENUM_SHIFT 0
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#define SCU_MPLL_DENUM_MASK 0x1f
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#define SCU_MPLL_NUM_SHIFT 5
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#define SCU_MPLL_NUM_MASK (0xff << SCU_MPLL_NUM_SHIFT)
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#define SCU_MPLL_POST_SHIFT 13
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#define SCU_MPLL_POST_MASK (0x3f << SCU_MPLL_POST_SHIFT)
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#define SCU_PCLK_DIV_SHIFT 23
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#define SCU_PCLK_DIV_MASK (7 << SCU_PCLK_DIV_SHIFT)
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#define SCU_HPLL_DENUM_SHIFT 0
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#define SCU_HPLL_DENUM_MASK 0x1f
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#define SCU_HPLL_NUM_SHIFT 5
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#define SCU_HPLL_NUM_MASK (0xff << SCU_HPLL_NUM_SHIFT)
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#define SCU_HPLL_POST_SHIFT 13
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#define SCU_HPLL_POST_MASK (0x3f << SCU_HPLL_POST_SHIFT)
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#define SCU_MACCLK_SHIFT 16
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#define SCU_MACCLK_MASK (7 << SCU_MACCLK_SHIFT)
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#define SCU_MISC2_RGMII_HPLL (1 << 23)
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#define SCU_MISC2_RGMII_CLKDIV_SHIFT 20
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#define SCU_MISC2_RGMII_CLKDIV_MASK (3 << SCU_MISC2_RGMII_CLKDIV_SHIFT)
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#define SCU_MISC2_RMII_MPLL (1 << 19)
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#define SCU_MISC2_RMII_CLKDIV_SHIFT 16
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#define SCU_MISC2_RMII_CLKDIV_MASK (3 << SCU_MISC2_RMII_CLKDIV_SHIFT)
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#define SCU_MISC2_UARTCLK_SHIFT 24
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#define SCU_MISC_D2PLL_OFF (1 << 4)
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#define SCU_MISC_UARTCLK_DIV13 (1 << 12)
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#define SCU_MISC_GCRT_USB20CLK (1 << 21)
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#define SCU_MICDS_MAC1RGMII_TXDLY_SHIFT 0
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#define SCU_MICDS_MAC1RGMII_TXDLY_MASK (0x3f\
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<< SCU_MICDS_MAC1RGMII_TXDLY_SHIFT)
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#define SCU_MICDS_MAC2RGMII_TXDLY_SHIFT 6
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#define SCU_MICDS_MAC2RGMII_TXDLY_MASK (0x3f\
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<< SCU_MICDS_MAC2RGMII_TXDLY_SHIFT)
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#define SCU_MICDS_MAC1RMII_RDLY_SHIFT 12
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#define SCU_MICDS_MAC1RMII_RDLY_MASK (0x3f << SCU_MICDS_MAC1RMII_RDLY_SHIFT)
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#define SCU_MICDS_MAC2RMII_RDLY_SHIFT 18
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#define SCU_MICDS_MAC2RMII_RDLY_MASK (0x3f << SCU_MICDS_MAC2RMII_RDLY_SHIFT)
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#define SCU_MICDS_MAC1RMII_TXFALL (1 << 24)
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#define SCU_MICDS_MAC2RMII_TXFALL (1 << 25)
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#define SCU_MICDS_RMII1_RCLKEN (1 << 29)
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#define SCU_MICDS_RMII2_RCLKEN (1 << 30)
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#define SCU_MICDS_RGMIIPLL (1 << 31)
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/*
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* SYSRESET is actually more like a Power register,
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* except that corresponding bit set to 1 means that
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* the peripheral is off.
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*/
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#define SCU_SYSRESET_XDMA (1 << 25)
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#define SCU_SYSRESET_MCTP (1 << 24)
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#define SCU_SYSRESET_ADC (1 << 23)
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#define SCU_SYSRESET_JTAG (1 << 22)
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#define SCU_SYSRESET_MIC (1 << 18)
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#define SCU_SYSRESET_SDIO (1 << 16)
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#define SCU_SYSRESET_USB11HOST (1 << 15)
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#define SCU_SYSRESET_USBHUB (1 << 14)
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#define SCU_SYSRESET_CRT (1 << 13)
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#define SCU_SYSRESET_MAC2 (1 << 12)
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#define SCU_SYSRESET_MAC1 (1 << 11)
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#define SCU_SYSRESET_PECI (1 << 10)
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#define SCU_SYSRESET_PWM (1 << 9)
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#define SCU_SYSRESET_PCI_VGA (1 << 8)
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#define SCU_SYSRESET_2D (1 << 7)
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#define SCU_SYSRESET_VIDEO (1 << 6)
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#define SCU_SYSRESET_LPC (1 << 5)
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#define SCU_SYSRESET_HAC (1 << 4)
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#define SCU_SYSRESET_USBHID (1 << 3)
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#define SCU_SYSRESET_I2C (1 << 2)
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#define SCU_SYSRESET_AHB (1 << 1)
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#define SCU_SYSRESET_SDRAM_WDT (1 << 0)
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/* Bits 16-27 in the register control pin functions for I2C devices 3-14 */
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#define SCU_PINMUX_CTRL5_I2C (1 << 16)
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/*
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* The values are grouped by function, not by register.
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* They are actually scattered across multiple loosely related registers.
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*/
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#define SCU_PIN_FUN_MAC1_MDC (1 << 30)
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#define SCU_PIN_FUN_MAC1_MDIO (1 << 31)
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#define SCU_PIN_FUN_MAC1_PHY_LINK (1 << 0)
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#define SCU_PIN_FUN_MAC2_MDIO (1 << 2)
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#define SCU_PIN_FUN_MAC2_PHY_LINK (1 << 1)
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#define SCU_PIN_FUN_SCL1 (1 << 12)
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#define SCU_PIN_FUN_SCL2 (1 << 14)
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#define SCU_PIN_FUN_SDA1 (1 << 13)
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#define SCU_PIN_FUN_SDA2 (1 << 15)
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#define SCU_CLKSTOP_MAC1 (1 << 20)
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#define SCU_CLKSTOP_MAC2 (1 << 21)
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#define SCU_D2PLL_EXT1_OFF (1 << 0)
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#define SCU_D2PLL_EXT1_BYPASS (1 << 1)
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#define SCU_D2PLL_EXT1_RESET (1 << 2)
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#define SCU_D2PLL_EXT1_MODE_SHIFT 3
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#define SCU_D2PLL_EXT1_MODE_MASK (3 << SCU_D2PLL_EXT1_MODE_SHIFT)
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#define SCU_D2PLL_EXT1_PARAM_SHIFT 5
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#define SCU_D2PLL_EXT1_PARAM_MASK (0x1ff << SCU_D2PLL_EXT1_PARAM_SHIFT)
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#define SCU_D2PLL_NUM_SHIFT 0
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#define SCU_D2PLL_NUM_MASK (0xff << SCU_D2PLL_NUM_SHIFT)
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#define SCU_D2PLL_DENUM_SHIFT 8
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#define SCU_D2PLL_DENUM_MASK (0x1f << SCU_D2PLL_DENUM_SHIFT)
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#define SCU_D2PLL_POST_SHIFT 13
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#define SCU_D2PLL_POST_MASK (0x3f << SCU_D2PLL_POST_SHIFT)
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#define SCU_D2PLL_ODIV_SHIFT 19
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#define SCU_D2PLL_ODIV_MASK (7 << SCU_D2PLL_ODIV_SHIFT)
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#define SCU_D2PLL_SIC_SHIFT 22
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#define SCU_D2PLL_SIC_MASK (0x1f << SCU_D2PLL_SIC_SHIFT)
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#define SCU_D2PLL_SIP_SHIFT 27
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#define SCU_D2PLL_SIP_MASK (0x1f << SCU_D2PLL_SIP_SHIFT)
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#define SCU_CLKDUTY_DCLK_SHIFT 0
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#define SCU_CLKDUTY_DCLK_MASK (0x3f << SCU_CLKDUTY_DCLK_SHIFT)
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#define SCU_CLKDUTY_RGMII1TXCK_SHIFT 8
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#define SCU_CLKDUTY_RGMII1TXCK_MASK (0x7f << SCU_CLKDUTY_RGMII1TXCK_SHIFT)
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#define SCU_CLKDUTY_RGMII2TXCK_SHIFT 16
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#define SCU_CLKDUTY_RGMII2TXCK_MASK (0x7f << SCU_CLKDUTY_RGMII2TXCK_SHIFT)
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#ifndef __ASSEMBLY__
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struct ast2500_clk_priv {
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struct ast2500_scu *scu;
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};
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struct ast2500_scu {
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u32 protection_key;
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u32 sysreset_ctrl1;
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u32 clk_sel1;
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u32 clk_stop_ctrl1;
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u32 freq_counter_ctrl;
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u32 freq_counter_cmp;
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u32 intr_ctrl;
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u32 d2_pll_param;
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u32 m_pll_param;
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u32 h_pll_param;
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u32 d_pll_param;
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u32 misc_ctrl1;
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u32 pci_config[3];
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u32 sysreset_status;
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u32 vga_handshake[2];
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u32 mac_clk_delay;
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u32 misc_ctrl2;
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u32 vga_scratch[8];
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u32 hwstrap;
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u32 rng_ctrl;
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u32 rng_data;
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u32 rev_id;
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u32 pinmux_ctrl[6];
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u32 reserved0;
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u32 extrst_sel;
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u32 pinmux_ctrl1[4];
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u32 reserved1[2];
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u32 mac_clk_delay_100M;
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u32 mac_clk_delay_10M;
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u32 wakeup_enable;
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u32 wakeup_control;
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u32 reserved2[3];
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u32 sysreset_ctrl2;
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u32 clk_sel2;
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u32 clk_stop_ctrl2;
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u32 freerun_counter;
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u32 freerun_counter_ext;
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u32 clk_duty_meas_ctrl;
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u32 clk_duty_meas_res;
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u32 reserved3[4];
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/* The next registers are not key-protected */
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struct ast2500_cpu2 {
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u32 ctrl;
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u32 base_addr[9];
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u32 cache_ctrl;
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} cpu2;
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u32 reserved4;
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u32 d_pll_ext_param[3];
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u32 d2_pll_ext_param[3];
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u32 mh_pll_ext_param;
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u32 reserved5;
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u32 chip_id[2];
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u32 reserved6[2];
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u32 uart_clk_ctrl;
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u32 reserved7[7];
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u32 pcie_config;
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u32 mmio_decode;
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u32 reloc_ctrl_decode[2];
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u32 mailbox_addr;
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u32 shared_sram_decode[2];
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u32 bmc_rev_id;
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u32 reserved8;
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u32 bmc_device_id;
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u32 reserved9[13];
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u32 clk_duty_sel;
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};
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/**
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* ast_get_clk() - get a pointer to Clock Driver
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*
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* @devp, OUT - pointer to Clock Driver
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* @return zero on success, error code (< 0) otherwise.
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*/
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int ast_get_clk(struct udevice **devp);
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/**
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* ast_get_scu() - get a pointer to SCU registers
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*
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* @return pointer to struct ast2500_scu on success, ERR_PTR otherwise
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*/
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void *ast_get_scu(void);
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/**
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* ast_scu_unlock() - unlock protected registers
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*
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* @scu, pointer to ast2500_scu
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*/
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void ast_scu_unlock(struct ast2500_scu *scu);
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/**
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* ast_scu_lock() - lock protected registers
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*
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* @scu, pointer to ast2500_scu
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*/
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void ast_scu_lock(struct ast2500_scu *scu);
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_ARCH_SCU_AST2500_H */
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