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![]() The DDR3 training code for Marvell A38X currently computes 1t timing when given board topology map of the Turris Omnia, but Omnia needs 2t. This patch adds support for enforcing the 2t timing in struct hws_topology_map, through a new enum hws_timing, which can assume following values: HWS_TIM_DEFAULT - default behaviour, compute whether to enable 2t from the number of CSs HWS_TIM_1T - enforce 1t HWS_TIM_2T - enforce 2t This patch also sets all the board topology maps (db-88f6820-amc, db-88f6820-gp, controlcenterdc and clearfog) to have timing set to HWS_TIM_DEFAULT. Signed-off-by: Marek Behun <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de> |
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db-88f6820-gp.c | ||
kwbimage.cfg | ||
MAINTAINERS | ||
Makefile | ||
README |
Update from original Marvell U-Boot to mainline U-Boot: ------------------------------------------------------- The resulting image including the SPL binary with the full DDR setup is "u-boot-spl.kwb". To update the SPI NOR flash, please use the following command: => sf probe;tftpboot 2000000 db-88f6820-gp/u-boot-spl.kwb;\ sf update 2000000 0 60000 Note that the original Marvell U-Boot seems to have problems with the "sf update" command. This does not work reliable. So here this command should be used: => sf probe;tftpboot 2000000 db-88f6820-gp/u-boot-spl.kwb;\ sf erase 0 60000;sf write 2000000 0 60000