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https://github.com/brain-hackers/u-boot-brain
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caa4daa2ae
We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
271 lines
6.9 KiB
C
271 lines
6.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2016 Google, Inc
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*
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* From coreboot src/soc/intel/broadwell/sata.c
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*/
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#include <common.h>
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#include <dm.h>
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#include <log.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/intel_regs.h>
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#include <asm/lpc_common.h>
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#include <asm/pch_common.h>
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#include <asm/pch_common.h>
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#include <asm/arch/pch.h>
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#include <linux/delay.h>
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struct sata_platdata {
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int port_map;
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uint port0_gen3_tx;
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uint port1_gen3_tx;
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uint port0_gen3_dtle;
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uint port1_gen3_dtle;
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/*
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* SATA DEVSLP Mux
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* 0 = port 0 DEVSLP on DEVSLP0/GPIO33
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* 1 = port 3 DEVSLP on DEVSLP0/GPIO33
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*/
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int devslp_mux;
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/*
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* DEVSLP Disable
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* 0: DEVSLP is enabled
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* 1: DEVSLP is disabled
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*/
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int devslp_disable;
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};
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static void broadwell_sata_init(struct udevice *dev)
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{
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struct sata_platdata *plat = dev_get_platdata(dev);
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u32 reg32;
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u8 *abar;
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u16 reg16;
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int port;
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debug("SATA: Initializing controller in AHCI mode.\n");
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/* Set timings */
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dm_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE);
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dm_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE);
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/* for AHCI, Port Enable is managed in memory mapped space */
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dm_pci_read_config16(dev, 0x92, ®16);
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reg16 &= ~0xf;
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reg16 |= 0x8000 | plat->port_map;
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dm_pci_write_config16(dev, 0x92, reg16);
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udelay(2);
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/* Setup register 98h */
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dm_pci_read_config32(dev, 0x98, ®32);
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reg32 &= ~((1 << 31) | (1 << 30));
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reg32 |= 1 << 23;
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reg32 |= 1 << 24; /* Enable MPHY Dynamic Power Gating */
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dm_pci_write_config32(dev, 0x98, reg32);
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/* Setup register 9Ch */
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reg16 = 0; /* Disable alternate ID */
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reg16 = 1 << 5; /* BWG step 12 */
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dm_pci_write_config16(dev, 0x9c, reg16);
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/* SATA Initialization register */
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reg32 = 0x183;
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reg32 |= (plat->port_map ^ 0xf) << 24;
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reg32 |= (plat->devslp_mux & 1) << 15;
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dm_pci_write_config32(dev, 0x94, reg32);
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/* Initialize AHCI memory-mapped space */
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dm_pci_read_config32(dev, PCI_BASE_ADDRESS_5, ®32);
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abar = (u8 *)reg32;
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debug("ABAR: %p\n", abar);
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/* CAP (HBA Capabilities) : enable power management */
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clrsetbits_le32(abar + 0x00, 0x00020060 /* SXS+EMS+PMS */,
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0x0c006000 /* PSC+SSC+SALP+SSS */ |
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1 << 18); /* SAM: SATA AHCI MODE ONLY */
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/* PI (Ports implemented) */
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writel(plat->port_map, abar + 0x0c);
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(void) readl(abar + 0x0c); /* Read back 1 */
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(void) readl(abar + 0x0c); /* Read back 2 */
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/* CAP2 (HBA Capabilities Extended)*/
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if (plat->devslp_disable) {
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clrbits_le32(abar + 0x24, 1 << 3);
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} else {
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/* Enable DEVSLP */
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setbits_le32(abar + 0x24, 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2);
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for (port = 0; port < 4; port++) {
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if (!(plat->port_map & (1 << port)))
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continue;
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/* DEVSLP DSP */
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setbits_le32(abar + 0x144 + (0x80 * port), 1 << 1);
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}
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}
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/* Static Power Gating for unused ports */
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reg32 = readl(RCB_REG(0x3a84));
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/* Port 3 and 2 disabled */
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if ((plat->port_map & ((1 << 3)|(1 << 2))) == 0)
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reg32 |= (1 << 24) | (1 << 26);
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/* Port 1 and 0 disabled */
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if ((plat->port_map & ((1 << 1)|(1 << 0))) == 0)
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reg32 |= (1 << 20) | (1 << 18);
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writel(reg32, RCB_REG(0x3a84));
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/* Set Gen3 Transmitter settings if needed */
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if (plat->port0_gen3_tx)
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pch_iobp_update(SATA_IOBP_SP0_SECRT88,
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~(SATA_SECRT88_VADJ_MASK <<
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SATA_SECRT88_VADJ_SHIFT),
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(plat->port0_gen3_tx &
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SATA_SECRT88_VADJ_MASK)
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<< SATA_SECRT88_VADJ_SHIFT);
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if (plat->port1_gen3_tx)
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pch_iobp_update(SATA_IOBP_SP1_SECRT88,
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~(SATA_SECRT88_VADJ_MASK <<
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SATA_SECRT88_VADJ_SHIFT),
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(plat->port1_gen3_tx &
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SATA_SECRT88_VADJ_MASK)
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<< SATA_SECRT88_VADJ_SHIFT);
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/* Set Gen3 DTLE DATA / EDGE registers if needed */
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if (plat->port0_gen3_dtle) {
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pch_iobp_update(SATA_IOBP_SP0DTLE_DATA,
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~(SATA_DTLE_MASK << SATA_DTLE_DATA_SHIFT),
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(plat->port0_gen3_dtle & SATA_DTLE_MASK)
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<< SATA_DTLE_DATA_SHIFT);
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pch_iobp_update(SATA_IOBP_SP0DTLE_EDGE,
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~(SATA_DTLE_MASK << SATA_DTLE_EDGE_SHIFT),
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(plat->port0_gen3_dtle & SATA_DTLE_MASK)
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<< SATA_DTLE_EDGE_SHIFT);
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}
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if (plat->port1_gen3_dtle) {
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pch_iobp_update(SATA_IOBP_SP1DTLE_DATA,
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~(SATA_DTLE_MASK << SATA_DTLE_DATA_SHIFT),
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(plat->port1_gen3_dtle & SATA_DTLE_MASK)
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<< SATA_DTLE_DATA_SHIFT);
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pch_iobp_update(SATA_IOBP_SP1DTLE_EDGE,
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~(SATA_DTLE_MASK << SATA_DTLE_EDGE_SHIFT),
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(plat->port1_gen3_dtle & SATA_DTLE_MASK)
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<< SATA_DTLE_EDGE_SHIFT);
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}
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/*
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* Additional Programming Requirements for Power Optimizer
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*/
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/* Step 1 */
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pch_common_sir_write(dev, 0x64, 0x883c9003);
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/* Step 2: SIR 68h[15:0] = 880Ah */
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reg32 = pch_common_sir_read(dev, 0x68);
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reg32 &= 0xffff0000;
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reg32 |= 0x880a;
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pch_common_sir_write(dev, 0x68, reg32);
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/* Step 3: SIR 60h[3] = 1 */
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reg32 = pch_common_sir_read(dev, 0x60);
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reg32 |= (1 << 3);
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pch_common_sir_write(dev, 0x60, reg32);
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/* Step 4: SIR 60h[0] = 1 */
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reg32 = pch_common_sir_read(dev, 0x60);
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reg32 |= (1 << 0);
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pch_common_sir_write(dev, 0x60, reg32);
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/* Step 5: SIR 60h[1] = 1 */
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reg32 = pch_common_sir_read(dev, 0x60);
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reg32 |= (1 << 1);
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pch_common_sir_write(dev, 0x60, reg32);
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/* Clock Gating */
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pch_common_sir_write(dev, 0x70, 0x3f00bf1f);
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pch_common_sir_write(dev, 0x54, 0xcf000f0f);
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pch_common_sir_write(dev, 0x58, 0x00190000);
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clrsetbits_le32(RCB_REG(0x333c), 0x00300000, 0x00c00000);
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dm_pci_read_config32(dev, 0x300, ®32);
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reg32 |= 1 << 17 | 1 << 16 | 1 << 19;
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reg32 |= 1 << 31 | 1 << 30 | 1 << 29;
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dm_pci_write_config32(dev, 0x300, reg32);
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dm_pci_read_config32(dev, 0x98, ®32);
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reg32 |= 1 << 29;
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dm_pci_write_config32(dev, 0x98, reg32);
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/* Register Lock */
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dm_pci_read_config32(dev, 0x9c, ®32);
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reg32 |= 1 << 31;
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dm_pci_write_config32(dev, 0x9c, reg32);
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}
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static int broadwell_sata_enable(struct udevice *dev)
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{
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struct sata_platdata *plat = dev_get_platdata(dev);
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struct gpio_desc desc;
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u16 map;
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int ret;
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/*
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* Set SATA controller mode early so the resource allocator can
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* properly assign IO/Memory resources for the controller.
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*/
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map = 0x0060;
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map |= (plat->port_map ^ 0x3f) << 8;
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dm_pci_write_config16(dev, 0x90, map);
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ret = gpio_request_by_name(dev, "reset-gpio", 0, &desc, GPIOD_IS_OUT);
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if (ret)
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return ret;
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return 0;
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}
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static int broadwell_sata_ofdata_to_platdata(struct udevice *dev)
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{
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struct sata_platdata *plat = dev_get_platdata(dev);
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const void *blob = gd->fdt_blob;
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int node = dev_of_offset(dev);
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plat->port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0);
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plat->port0_gen3_tx = fdtdec_get_int(blob, node,
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"intel,sata-port0-gen3-tx", 0);
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return 0;
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}
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static int broadwell_sata_probe(struct udevice *dev)
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{
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if (!(gd->flags & GD_FLG_RELOC))
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return broadwell_sata_enable(dev);
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else
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broadwell_sata_init(dev);
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return 0;
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}
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static const struct udevice_id broadwell_ahci_ids[] = {
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{ .compatible = "intel,wildcatpoint-ahci" },
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{ }
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};
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U_BOOT_DRIVER(ahci_broadwell_drv) = {
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.name = "ahci_broadwell",
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.id = UCLASS_AHCI,
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.of_match = broadwell_ahci_ids,
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.ofdata_to_platdata = broadwell_sata_ofdata_to_platdata,
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.probe = broadwell_sata_probe,
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.plat_auto = sizeof(struct sata_platdata),
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};
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