mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 10:46:15 +09:00
61b29b8268
At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
97 lines
2.0 KiB
C
97 lines
2.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2015 Google, Inc
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*/
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#include <clk.h>
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#include <common.h>
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#include <dm.h>
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#include <asm/arch-rockchip/clock.h>
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#include <dt-bindings/clock/rk3288-cru.h>
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#include <linux/err.h>
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#include <power/regulator.h>
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/*
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* We should increase the DDR voltage to 1.2V using the PWM regulator.
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* There is a U-Boot driver for this but it may need to add support for the
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* 'voltage-table' property.
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*/
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#ifndef CONFIG_SPL_BUILD
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#if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
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static int veyron_init(void)
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{
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struct udevice *dev;
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struct clk clk;
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int ret;
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ret = regulator_get_by_platname("vdd_arm", &dev);
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if (ret) {
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debug("Cannot set regulator name\n");
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return ret;
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}
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/* Slowly raise to max CPU voltage to prevent overshoot */
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ret = regulator_set_value(dev, 1200000);
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if (ret)
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return ret;
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udelay(175); /* Must wait for voltage to stabilize, 2mV/us */
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ret = regulator_set_value(dev, 1400000);
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if (ret)
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return ret;
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udelay(100); /* Must wait for voltage to stabilize, 2mV/us */
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ret = rockchip_get_clk(&clk.dev);
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if (ret)
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return ret;
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clk.id = PLL_APLL;
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ret = clk_set_rate(&clk, 1800000000);
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if (IS_ERR_VALUE(ret))
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return ret;
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ret = regulator_get_by_platname("vcc33_sd", &dev);
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if (ret) {
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debug("Cannot get regulator name\n");
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return ret;
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}
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ret = regulator_set_value(dev, 3300000);
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if (ret)
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return ret;
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ret = regulators_enable_boot_on(false);
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if (ret) {
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debug("%s: Cannot enable boot on regulators\n", __func__);
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return ret;
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}
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return 0;
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}
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#endif
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int board_early_init_f(void)
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{
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struct udevice *dev;
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int ret;
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#if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
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if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) {
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ret = veyron_init();
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if (ret)
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return ret;
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}
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#endif
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/*
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* This init is done in SPL, but when chain-loading U-Boot SPL will
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* have been skipped. Allow the clock driver to check if it needs
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* setting up.
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*/
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ret = rockchip_get_clk(&dev);
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if (ret) {
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debug("CLK init failed: %d\n", ret);
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return ret;
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}
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return 0;
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}
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#endif
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