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![Masahiro Yamada](/assets/img/avatar_default.png)
Add basic clock data for Socionext's new SoC PXs3. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
80 lines
1.8 KiB
C
80 lines
1.8 KiB
C
/*
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* Copyright (C) 2016 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CLK_UNIPHIER_H__
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#define __CLK_UNIPHIER_H__
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#include <linux/kernel.h>
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#include <linux/types.h>
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#define UNIPHIER_CLK_MUX_MAX_PARENTS 8
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#define UNIPHIER_CLK_TYPE_END 0
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#define UNIPHIER_CLK_TYPE_FIXED_RATE 2
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#define UNIPHIER_CLK_TYPE_GATE 3
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#define UNIPHIER_CLK_TYPE_MUX 4
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#define UNIPHIER_CLK_ID_INVALID (U8_MAX)
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struct uniphier_clk_fixed_rate_data {
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unsigned long fixed_rate;
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};
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struct uniphier_clk_gate_data {
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u8 parent_id;
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u16 reg;
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u8 bit;
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};
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struct uniphier_clk_mux_data {
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u8 parent_ids[UNIPHIER_CLK_MUX_MAX_PARENTS];
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u8 num_parents;
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u16 reg;
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u32 masks[UNIPHIER_CLK_MUX_MAX_PARENTS];
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u32 vals[UNIPHIER_CLK_MUX_MAX_PARENTS];
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};
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struct uniphier_clk_data {
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u8 type;
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u8 id;
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union {
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struct uniphier_clk_fixed_rate_data rate;
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struct uniphier_clk_gate_data gate;
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struct uniphier_clk_mux_data mux;
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} data;
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};
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#define UNIPHIER_CLK_RATE(_id, _rate) \
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{ \
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.type = UNIPHIER_CLK_TYPE_FIXED_RATE, \
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.id = (_id), \
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.data.rate = { \
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.fixed_rate = (_rate), \
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}, \
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}
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#define UNIPHIER_CLK_GATE(_id, _parent, _reg, _bit) \
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{ \
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.type = UNIPHIER_CLK_TYPE_GATE, \
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.id = (_id), \
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.data.gate = { \
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.parent_id = (_parent), \
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.reg = (_reg), \
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.bit = (_bit), \
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}, \
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}
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#define UNIPHIER_CLK_GATE_SIMPLE(_id, _reg, _bit) \
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UNIPHIER_CLK_GATE(_id, UNIPHIER_CLK_ID_INVALID, _reg, _bit)
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extern const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[];
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extern const struct uniphier_clk_data uniphier_ld20_sys_clk_data[];
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extern const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[];
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extern const struct uniphier_clk_data uniphier_mio_clk_data[];
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#endif /* __CLK_UNIPHIER_H__ */
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