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https://github.com/brain-hackers/u-boot-brain
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![Hans-Christian Egtvedt](/assets/img/avatar_default.png)
This adds a driver for the SPI controller found on most AT91 and AVR32 chips, implementing the new SPI API. Changed in v4: - Update to new API - Handle zero-length transfers appropriately. The user may send a zero-length SPI transfer with SPI_XFER_END set in order to deactivate the chip select after a series of transfers with chip select active. This is useful e.g. when polling the status register of DataFlash. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
211 lines
4.4 KiB
C
211 lines
4.4 KiB
C
/*
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* Copyright (C) 2007 Atmel Corporation
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <spi.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/memory-map.h>
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#include "atmel_spi.h"
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void spi_init()
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{
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}
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struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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unsigned int max_hz, unsigned int mode)
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{
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struct atmel_spi_slave *as;
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unsigned int scbr;
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u32 csrx;
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void *regs;
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if (cs > 3 || !spi_cs_is_valid(bus, cs))
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return NULL;
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switch (bus) {
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case 0:
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regs = (void *)SPI0_BASE;
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break;
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#ifdef SPI1_BASE
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case 1:
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regs = (void *)SPI1_BASE;
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break;
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#endif
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#ifdef SPI2_BASE
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case 2:
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regs = (void *)SPI2_BASE;
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break;
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#endif
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#ifdef SPI3_BASE
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case 3:
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regs = (void *)SPI3_BASE;
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break;
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#endif
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default:
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return NULL;
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}
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scbr = (get_spi_clk_rate(bus) + max_hz - 1) / max_hz;
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if (scbr > ATMEL_SPI_CSRx_SCBR_MAX)
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/* Too low max SCK rate */
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return NULL;
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if (scbr < 1)
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scbr = 1;
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csrx = ATMEL_SPI_CSRx_SCBR(scbr);
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csrx |= ATMEL_SPI_CSRx_BITS(ATMEL_SPI_BITS_8);
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if (!(mode & SPI_CPHA))
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csrx |= ATMEL_SPI_CSRx_NCPHA;
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if (mode & SPI_CPOL)
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csrx |= ATMEL_SPI_CSRx_CPOL;
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as = malloc(sizeof(struct atmel_spi_slave));
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if (!as)
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return NULL;
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as->slave.bus = bus;
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as->slave.cs = cs;
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as->regs = regs;
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as->mr = ATMEL_SPI_MR_MSTR | ATMEL_SPI_MR_MODFDIS
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| ATMEL_SPI_MR_PCS(~(1 << cs) & 0xf);
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spi_writel(as, CSR(cs), csrx);
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return &as->slave;
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}
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void spi_free_slave(struct spi_slave *slave)
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{
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struct atmel_spi_slave *as = to_atmel_spi(slave);
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free(as);
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}
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int spi_claim_bus(struct spi_slave *slave)
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{
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struct atmel_spi_slave *as = to_atmel_spi(slave);
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/* Enable the SPI hardware */
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spi_writel(as, CR, ATMEL_SPI_CR_SPIEN);
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/*
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* Select the slave. This should set SCK to the correct
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* initial state, etc.
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*/
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spi_writel(as, MR, as->mr);
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return 0;
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}
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void spi_release_bus(struct spi_slave *slave)
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{
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struct atmel_spi_slave *as = to_atmel_spi(slave);
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/* Disable the SPI hardware */
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spi_writel(as, CR, ATMEL_SPI_CR_SPIDIS);
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}
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int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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struct atmel_spi_slave *as = to_atmel_spi(slave);
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unsigned int len_tx;
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unsigned int len_rx;
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unsigned int len;
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int ret;
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u32 status;
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const u8 *txp = dout;
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u8 *rxp = din;
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u8 value;
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ret = 0;
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if (bitlen == 0)
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/* Finish any previously submitted transfers */
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goto out;
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/*
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* TODO: The controller can do non-multiple-of-8 bit
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* transfers, but this driver currently doesn't support it.
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*
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* It's also not clear how such transfers are supposed to be
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* represented as a stream of bytes...this is a limitation of
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* the current SPI interface.
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*/
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if (bitlen % 8) {
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/* Errors always terminate an ongoing transfer */
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flags |= SPI_XFER_END;
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goto out;
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}
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len = bitlen / 8;
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/*
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* The controller can do automatic CS control, but it is
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* somewhat quirky, and it doesn't really buy us much anyway
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* in the context of U-Boot.
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*/
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if (flags & SPI_XFER_BEGIN)
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spi_cs_activate(slave);
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for (len_tx = 0, len_rx = 0; len_rx < len; ) {
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status = spi_readl(as, SR);
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if (status & ATMEL_SPI_SR_OVRES)
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return -1;
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if (len_tx < len && (status & ATMEL_SPI_SR_TDRE)) {
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if (txp)
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value = *txp++;
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else
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value = 0;
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spi_writel(as, TDR, value);
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len_tx++;
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}
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if (status & ATMEL_SPI_SR_RDRF) {
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value = spi_readl(as, RDR);
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if (rxp)
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*rxp++ = value;
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len_rx++;
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}
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}
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out:
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if (flags & SPI_XFER_END) {
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/*
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* Wait until the transfer is completely done before
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* we deactivate CS.
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*/
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do {
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status = spi_readl(as, SR);
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} while (!(status & ATMEL_SPI_SR_TXEMPTY));
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spi_cs_deactivate(slave);
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}
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return 0;
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}
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