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https://github.com/brain-hackers/u-boot-brain
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![Peter Tyser](/assets/img/avatar_default.png)
PPC boards are the only users of the current FPGA code which is littered with manual relocation fixups. Now that proper relocation is supported for PPC boards, remove FPGA manual relocation. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
211 lines
5.3 KiB
C
211 lines
5.3 KiB
C
/*
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* (C) Copyright 2006
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* Heiko Schocher, hs@denx.de
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* Based on ACE1XK.c
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <common.h> /* core U-Boot definitions */
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#include <altera.h>
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#include <ACEX1K.h> /* ACEX device family */
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/* Define FPGA_DEBUG to get debug printf's */
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#ifdef FPGA_DEBUG
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#define PRINTF(fmt,args...) printf (fmt ,##args)
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#else
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#define PRINTF(fmt,args...)
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#endif
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/* Note: The assumption is that we cannot possibly run fast enough to
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* overrun the device (the Slave Parallel mode can free run at 50MHz).
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* If there is a need to operate slower, define CONFIG_FPGA_DELAY in
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* the board config file to slow things down.
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*/
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#ifndef CONFIG_FPGA_DELAY
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#define CONFIG_FPGA_DELAY()
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#endif
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#ifndef CONFIG_SYS_FPGA_WAIT
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#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/10 /* 100 ms */
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#endif
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static int CYC2_ps_load( Altera_desc *desc, void *buf, size_t bsize );
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static int CYC2_ps_dump( Altera_desc *desc, void *buf, size_t bsize );
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/* static int CYC2_ps_info( Altera_desc *desc ); */
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/* ------------------------------------------------------------------------- */
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/* CYCLON2 Generic Implementation */
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int CYC2_load (Altera_desc * desc, void *buf, size_t bsize)
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{
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int ret_val = FPGA_FAIL;
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switch (desc->iface) {
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case passive_serial:
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PRINTF ("%s: Launching Passive Serial Loader\n", __FUNCTION__);
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ret_val = CYC2_ps_load (desc, buf, bsize);
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break;
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/* Add new interface types here */
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default:
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printf ("%s: Unsupported interface type, %d\n",
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__FUNCTION__, desc->iface);
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}
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return ret_val;
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}
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int CYC2_dump (Altera_desc * desc, void *buf, size_t bsize)
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{
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int ret_val = FPGA_FAIL;
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switch (desc->iface) {
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case passive_serial:
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PRINTF ("%s: Launching Passive Serial Dump\n", __FUNCTION__);
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ret_val = CYC2_ps_dump (desc, buf, bsize);
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break;
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/* Add new interface types here */
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default:
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printf ("%s: Unsupported interface type, %d\n",
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__FUNCTION__, desc->iface);
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}
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return ret_val;
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}
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int CYC2_info( Altera_desc *desc )
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{
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return FPGA_SUCCESS;
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}
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/* ------------------------------------------------------------------------- */
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/* CYCLON2 Passive Serial Generic Implementation */
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static int CYC2_ps_load (Altera_desc * desc, void *buf, size_t bsize)
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{
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int ret_val = FPGA_FAIL; /* assume the worst */
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Altera_CYC2_Passive_Serial_fns *fn = desc->iface_fns;
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int ret = 0;
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PRINTF ("%s: start with interface functions @ 0x%p\n",
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__FUNCTION__, fn);
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if (fn) {
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int cookie = desc->cookie; /* make a local copy */
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unsigned long ts; /* timestamp */
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PRINTF ("%s: Function Table:\n"
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"ptr:\t0x%p\n"
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"struct: 0x%p\n"
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"config:\t0x%p\n"
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"status:\t0x%p\n"
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"write:\t0x%p\n"
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"done:\t0x%p\n\n",
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__FUNCTION__, &fn, fn, fn->config, fn->status,
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fn->write, fn->done);
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#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
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printf ("Loading FPGA Device %d...", cookie);
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#endif
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/*
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* Run the pre configuration function if there is one.
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*/
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if (*fn->pre) {
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(*fn->pre) (cookie);
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}
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/* Establish the initial state */
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(*fn->config) (TRUE, TRUE, cookie); /* Assert nCONFIG */
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udelay(2); /* T_cfg > 2us */
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/* Wait for nSTATUS to be asserted */
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ts = get_timer (0); /* get current time */
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do {
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CONFIG_FPGA_DELAY ();
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if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
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puts ("** Timeout waiting for STATUS to go high.\n");
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(*fn->abort) (cookie);
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return FPGA_FAIL;
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}
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} while (!(*fn->status) (cookie));
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/* Get ready for the burn */
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CONFIG_FPGA_DELAY ();
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ret = (*fn->write) (buf, bsize, TRUE, cookie);
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if (ret) {
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puts ("** Write failed.\n");
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(*fn->abort) (cookie);
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return FPGA_FAIL;
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}
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#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
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puts(" OK? ...");
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#endif
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CONFIG_FPGA_DELAY ();
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#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
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putc (' '); /* terminate the dotted line */
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#endif
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/*
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* Checking FPGA's CONF_DONE signal - correctly booted ?
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*/
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if ( ! (*fn->done) (cookie) ) {
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puts ("** Booting failed! CONF_DONE is still deasserted.\n");
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(*fn->abort) (cookie);
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return (FPGA_FAIL);
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}
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#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
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puts(" OK\n");
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#endif
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ret_val = FPGA_SUCCESS;
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#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
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if (ret_val == FPGA_SUCCESS) {
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puts ("Done.\n");
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}
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else {
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puts ("Fail.\n");
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}
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#endif
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(*fn->post) (cookie);
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} else {
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printf ("%s: NULL Interface function table!\n", __FUNCTION__);
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}
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return ret_val;
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}
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static int CYC2_ps_dump (Altera_desc * desc, void *buf, size_t bsize)
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{
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/* Readback is only available through the Slave Parallel and */
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/* boundary-scan interfaces. */
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printf ("%s: Passive Serial Dumping is unavailable\n",
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__FUNCTION__);
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return FPGA_FAIL;
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}
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