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https://github.com/brain-hackers/u-boot-brain
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67f99f970f
Platform knows whether MRC cache is implemented, but using it can be a choice of a specific board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
29 lines
619 B
Plaintext
29 lines
619 B
Plaintext
#
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# Copyright (C) 2015 Google, Inc
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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config INTEL_BAYTRAIL
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bool
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select HAVE_FSP if !EFI
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select ARCH_MISC_INIT if !EFI
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imply ENV_IS_IN_SPI_FLASH
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imply HAVE_INTEL_ME if !EFI
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imply ENABLE_MRC_CACHE
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if INTEL_BAYTRAIL
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config INTERNAL_UART
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bool "Enable the SoC integrated legacy UART"
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help
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There is a legacy UART integrated into the Bay Trail SoC.
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A maximum baud rate of 115200 bps is supported. For this
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reason, it is recommended that the UART port be used for
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debug purposes only, eg: U-Boot console.
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config DEBUG_UART
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bool
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select DEBUG_UART_BOARD_INIT
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endif
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