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https://github.com/brain-hackers/u-boot-brain
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49b633b3d3
J6 EVM can be built with UART3 as console, but currently there's nothing muxing UART3 correctly. Likely this only works because, based on commit log, author was only testing with UART3 boot and - I assume - ROM code leave UART3 correctly muxed in that case. If we want to boot from MMC and still use UART3 as console, then we need to mux those signals correctly. Signed-off-by: Felipe Balbi <balbi@ti.com>
72 lines
2.8 KiB
C
72 lines
2.8 KiB
C
/*
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* (C) Copyright 2013
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* Texas Instruments Incorporated, <www.ti.com>
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*
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* Sricharan R <r.sricharan@ti.com>
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* Nishant Kamat <nskamat@ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _MUX_DATA_DRA7XX_H_
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#define _MUX_DATA_DRA7XX_H_
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#include <asm/arch/mux_dra7xx.h>
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const struct pad_conf_entry core_padconf_array_essential[] = {
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{MMC1_CLK, (IEN | PTU | PDIS | M0)}, /* MMC1_CLK */
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{MMC1_CMD, (IEN | PTU | PDIS | M0)}, /* MMC1_CMD */
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{MMC1_DAT0, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT0 */
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{MMC1_DAT1, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT1 */
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{MMC1_DAT2, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT2 */
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{MMC1_DAT3, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT3 */
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{MMC1_SDCD, (FSC | IEN | PTU | PDIS | M0)}, /* MMC1_SDCD */
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{MMC1_SDWP, (FSC | IEN | PTD | PEN | M14)}, /* MMC1_SDWP */
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{GPMC_A19, (IEN | PTU | PDIS | M1)}, /* mmc2_dat4 */
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{GPMC_A20, (IEN | PTU | PDIS | M1)}, /* mmc2_dat5 */
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{GPMC_A21, (IEN | PTU | PDIS | M1)}, /* mmc2_dat6 */
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{GPMC_A22, (IEN | PTU | PDIS | M1)}, /* mmc2_dat7 */
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{GPMC_A23, (IEN | PTU | PDIS | M1)}, /* mmc2_clk */
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{GPMC_A24, (IEN | PTU | PDIS | M1)}, /* mmc2_dat0 */
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{GPMC_A25, (IEN | PTU | PDIS | M1)}, /* mmc2_dat1 */
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{GPMC_A26, (IEN | PTU | PDIS | M1)}, /* mmc2_dat2 */
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{GPMC_A27, (IEN | PTU | PDIS | M1)}, /* mmc2_dat3 */
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{GPMC_CS1, (IEN | PTU | PDIS | M1)}, /* mmm2_cmd */
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#if (CONFIG_CONS_INDEX == 1)
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{UART1_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_RXD */
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{UART1_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_TXD */
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{UART1_CTSN, (IEN | PTU | PDIS | M3)}, /* UART1_CTSN */
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{UART1_RTSN, (IEN | PTU | PDIS | M3)}, /* UART1_RTSN */
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#elif (CONFIG_CONS_INDEX == 3)
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{UART3_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_RXD */
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{UART3_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_TXD */
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#endif
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{I2C1_SDA, (IEN | PTU | PDIS | M0)}, /* I2C1_SDA */
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{I2C1_SCL, (IEN | PTU | PDIS | M0)}, /* I2C1_SCL */
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{MDIO_MCLK, (PTU | PEN | M0)}, /* MDIO_MCLK */
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{MDIO_D, (IEN | PTU | PEN | M0)}, /* MDIO_D */
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{RGMII0_TXC, (M0) },
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{RGMII0_TXCTL, (M0) },
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{RGMII0_TXD3, (M0) },
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{RGMII0_TXD2, (M0) },
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{RGMII0_TXD1, (M0) },
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{RGMII0_TXD0, (M0) },
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{RGMII0_RXC, (IEN | M0) },
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{RGMII0_RXCTL, (IEN | M0) },
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{RGMII0_RXD3, (IEN | M0) },
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{RGMII0_RXD2, (IEN | M0) },
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{RGMII0_RXD1, (IEN | M0) },
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{RGMII0_RXD0, (IEN | M0) },
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{GPMC_A13, (IEN | PDIS | M1)}, /* QSPI1_RTCLK */
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{GPMC_A14, (IEN | PDIS | M1)}, /* QSPI1_D[3] */
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{GPMC_A15, (IEN | PDIS | M1)}, /* QSPI1_D[2] */
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{GPMC_A16, (IEN | PDIS | M1)}, /* QSPI1_D[1] */
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{GPMC_A17, (IEN | PDIS | M1)}, /* QSPI1_D[0] */
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{GPMC_A18, (M1)}, /* QSPI1_SCLK */
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{GPMC_A3, (IEN | PDIS | M1)}, /* QSPI1_CS2 */
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{GPMC_A4, (IEN | PDIS | M1)}, /* QSPI1_CS3 */
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{GPMC_CS2, (IEN | PTU | PDIS | M1)}, /* QSPI1_CS0 */
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{GPMC_CS3, (IEN | PTU | PDIS | M1)}, /* QSPI1_CS1*/
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{USB2_DRVVBUS, (M0 | IEN | FSC) },
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};
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#endif /* _MUX_DATA_DRA7XX_H_ */
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