mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-08 04:06:15 +09:00
4e7f8de426
- Use - instead of @ for OPP tables - Add input-delay properties to Cadence eMMC nodes - Restore full license text because code-diff is annoying - Fix NAND compatible strings Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
685 lines
16 KiB
Plaintext
685 lines
16 KiB
Plaintext
/*
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* Device Tree Source for UniPhier PXs2 SoC
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*
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* Copyright (C) 2015-2016 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/ {
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compatible = "socionext,uniphier-pxs2";
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0>;
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clocks = <&sys_clk 32>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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operating-points-v2 = <&cpu_opp>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <1>;
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clocks = <&sys_clk 32>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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operating-points-v2 = <&cpu_opp>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <2>;
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clocks = <&sys_clk 32>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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operating-points-v2 = <&cpu_opp>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <3>;
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clocks = <&sys_clk 32>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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operating-points-v2 = <&cpu_opp>;
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};
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};
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cpu_opp: opp_table {
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compatible = "operating-points-v2";
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opp-shared;
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opp-100000000 {
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opp-hz = /bits/ 64 <100000000>;
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clock-latency-ns = <300>;
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};
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opp-150000000 {
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opp-hz = /bits/ 64 <150000000>;
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clock-latency-ns = <300>;
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};
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opp-200000000 {
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opp-hz = /bits/ 64 <200000000>;
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clock-latency-ns = <300>;
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};
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opp-300000000 {
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opp-hz = /bits/ 64 <300000000>;
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clock-latency-ns = <300>;
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};
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opp-400000000 {
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opp-hz = /bits/ 64 <400000000>;
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clock-latency-ns = <300>;
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};
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opp-600000000 {
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opp-hz = /bits/ 64 <600000000>;
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clock-latency-ns = <300>;
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};
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opp-800000000 {
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opp-hz = /bits/ 64 <800000000>;
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clock-latency-ns = <300>;
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};
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opp-1200000000 {
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opp-hz = /bits/ 64 <1200000000>;
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clock-latency-ns = <300>;
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};
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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clocks {
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refclk: ref {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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};
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arm_timer_clk: arm_timer_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <50000000>;
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};
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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interrupt-parent = <&intc>;
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u-boot,dm-pre-reloc;
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l2: l2-cache@500c0000 {
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compatible = "socionext,uniphier-system-cache";
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reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
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<0x506c0000 0x400>;
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interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
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cache-unified;
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cache-size = <(1280 * 1024)>;
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cache-sets = <512>;
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cache-line-size = <128>;
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cache-level = <2>;
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};
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serial0: serial@54006800 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006800 0x40>;
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interrupts = <0 33 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart0>;
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clocks = <&peri_clk 0>;
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clock-frequency = <88900000>;
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};
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serial1: serial@54006900 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006900 0x40>;
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interrupts = <0 35 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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clocks = <&peri_clk 1>;
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clock-frequency = <88900000>;
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};
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serial2: serial@54006a00 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006a00 0x40>;
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interrupts = <0 37 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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clocks = <&peri_clk 2>;
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clock-frequency = <88900000>;
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};
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serial3: serial@54006b00 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006b00 0x40>;
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interrupts = <0 177 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3>;
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clocks = <&peri_clk 3>;
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clock-frequency = <88900000>;
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};
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port0x: gpio@55000008 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000008 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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port1x: gpio@55000010 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000010 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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port2x: gpio@55000018 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000018 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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port3x: gpio@55000020 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000020 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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port4: gpio@55000028 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000028 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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port5x: gpio@55000030 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000030 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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port6x: gpio@55000038 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000038 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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port7x: gpio@55000040 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000040 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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port8x: gpio@55000048 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000048 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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port9x: gpio@55000050 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000050 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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port10x: gpio@55000058 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000058 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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port12x: gpio@55000068 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000068 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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port13x: gpio@55000070 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000070 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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port14x: gpio@55000078 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000078 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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port15x: gpio@55000080 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000080 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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port16x: gpio@55000088 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x55000088 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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port17x: gpio@550000a0 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x550000a0 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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port18x: gpio@550000a8 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x550000a8 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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port19x: gpio@550000b0 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x550000b0 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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port20x: gpio@550000b8 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x550000b8 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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port21x: gpio@550000c0 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x550000c0 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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port22x: gpio@550000c8 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x550000c8 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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port23x: gpio@550000d0 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x550000d0 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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port24x: gpio@550000d8 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x550000d8 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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port25x: gpio@550000e0 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x550000e0 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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port26x: gpio@550000e8 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x550000e8 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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port27x: gpio@550000f0 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x550000f0 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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port28x: gpio@550000f8 {
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compatible = "socionext,uniphier-gpio";
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reg = <0x550000f8 0x8>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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i2c0: i2c@58780000 {
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compatible = "socionext,uniphier-fi2c";
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status = "disabled";
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reg = <0x58780000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 41 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c0>;
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clocks = <&peri_clk 4>;
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clock-frequency = <100000>;
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};
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i2c1: i2c@58781000 {
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compatible = "socionext,uniphier-fi2c";
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status = "disabled";
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reg = <0x58781000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 42 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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clocks = <&peri_clk 5>;
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clock-frequency = <100000>;
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};
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i2c2: i2c@58782000 {
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compatible = "socionext,uniphier-fi2c";
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status = "disabled";
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reg = <0x58782000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 43 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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clocks = <&peri_clk 6>;
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clock-frequency = <100000>;
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};
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i2c3: i2c@58783000 {
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compatible = "socionext,uniphier-fi2c";
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status = "disabled";
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reg = <0x58783000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 44 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3>;
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clocks = <&peri_clk 7>;
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clock-frequency = <100000>;
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};
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/* chip-internal connection for DMD */
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i2c4: i2c@58784000 {
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compatible = "socionext,uniphier-fi2c";
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reg = <0x58784000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 45 4>;
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clocks = <&peri_clk 8>;
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clock-frequency = <400000>;
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};
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/* chip-internal connection for STM */
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i2c5: i2c@58785000 {
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compatible = "socionext,uniphier-fi2c";
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reg = <0x58785000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 25 4>;
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clocks = <&peri_clk 9>;
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clock-frequency = <400000>;
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};
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/* chip-internal connection for HDMI */
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i2c6: i2c@58786000 {
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compatible = "socionext,uniphier-fi2c";
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reg = <0x58786000 0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 26 4>;
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clocks = <&peri_clk 10>;
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clock-frequency = <400000>;
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};
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system_bus: system-bus@58c00000 {
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compatible = "socionext,uniphier-system-bus";
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status = "disabled";
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reg = <0x58c00000 0x400>;
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#address-cells = <2>;
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#size-cells = <1>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_system_bus>;
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};
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smpctrl@59800000 {
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compatible = "socionext,uniphier-smpctrl";
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reg = <0x59801000 0x400>;
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};
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sdctrl@59810000 {
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compatible = "socionext,uniphier-pxs2-sdctrl",
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"simple-mfd", "syscon";
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reg = <0x59810000 0x800>;
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u-boot,dm-pre-reloc;
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sd_clk: clock {
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compatible = "socionext,uniphier-pxs2-sd-clock";
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
sd_rst: reset {
|
|
compatible = "socionext,uniphier-pxs2-sd-reset";
|
|
#reset-cells = <1>;
|
|
};
|
|
};
|
|
|
|
perictrl@59820000 {
|
|
compatible = "socionext,uniphier-pxs2-perictrl",
|
|
"simple-mfd", "syscon";
|
|
reg = <0x59820000 0x200>;
|
|
|
|
peri_clk: clock {
|
|
compatible = "socionext,uniphier-pxs2-peri-clock";
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
peri_rst: reset {
|
|
compatible = "socionext,uniphier-pxs2-peri-reset";
|
|
#reset-cells = <1>;
|
|
};
|
|
};
|
|
|
|
emmc: sdhc@5a000000 {
|
|
compatible = "socionext,uniphier-sdhc";
|
|
status = "disabled";
|
|
reg = <0x5a000000 0x800>;
|
|
interrupts = <0 78 4>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_emmc>;
|
|
clocks = <&sd_clk 1>;
|
|
reset-names = "host";
|
|
resets = <&sd_rst 1>;
|
|
bus-width = <8>;
|
|
non-removable;
|
|
cap-mmc-highspeed;
|
|
cap-mmc-hw-reset;
|
|
no-3-3-v;
|
|
};
|
|
|
|
sd: sdhc@5a400000 {
|
|
compatible = "socionext,uniphier-sdhc";
|
|
status = "disabled";
|
|
reg = <0x5a400000 0x800>;
|
|
interrupts = <0 76 4>;
|
|
pinctrl-names = "default", "1.8v";
|
|
pinctrl-0 = <&pinctrl_sd>;
|
|
pinctrl-1 = <&pinctrl_sd_1v8>;
|
|
clocks = <&sd_clk 0>;
|
|
reset-names = "host";
|
|
resets = <&sd_rst 0>;
|
|
bus-width = <4>;
|
|
cap-sd-highspeed;
|
|
sd-uhs-sdr12;
|
|
sd-uhs-sdr25;
|
|
sd-uhs-sdr50;
|
|
};
|
|
|
|
soc-glue@5f800000 {
|
|
compatible = "socionext,uniphier-pxs2-soc-glue",
|
|
"simple-mfd", "syscon";
|
|
reg = <0x5f800000 0x2000>;
|
|
u-boot,dm-pre-reloc;
|
|
|
|
pinctrl: pinctrl {
|
|
compatible = "socionext,uniphier-pxs2-pinctrl";
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
};
|
|
|
|
aidet@5fc20000 {
|
|
compatible = "simple-mfd", "syscon";
|
|
reg = <0x5fc20000 0x200>;
|
|
};
|
|
|
|
timer@60000200 {
|
|
compatible = "arm,cortex-a9-global-timer";
|
|
reg = <0x60000200 0x20>;
|
|
interrupts = <1 11 0xf04>;
|
|
clocks = <&arm_timer_clk>;
|
|
};
|
|
|
|
timer@60000600 {
|
|
compatible = "arm,cortex-a9-twd-timer";
|
|
reg = <0x60000600 0x20>;
|
|
interrupts = <1 13 0xf04>;
|
|
clocks = <&arm_timer_clk>;
|
|
};
|
|
|
|
intc: interrupt-controller@60001000 {
|
|
compatible = "arm,cortex-a9-gic";
|
|
reg = <0x60001000 0x1000>,
|
|
<0x60000100 0x100>;
|
|
#interrupt-cells = <3>;
|
|
interrupt-controller;
|
|
};
|
|
|
|
sysctrl@61840000 {
|
|
compatible = "socionext,uniphier-pxs2-sysctrl",
|
|
"simple-mfd", "syscon";
|
|
reg = <0x61840000 0x10000>;
|
|
|
|
sys_clk: clock {
|
|
compatible = "socionext,uniphier-pxs2-clock";
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
sys_rst: reset {
|
|
compatible = "socionext,uniphier-pxs2-reset";
|
|
#reset-cells = <1>;
|
|
};
|
|
};
|
|
|
|
usb0: usb@65b00000 {
|
|
compatible = "socionext,uniphier-pxs2-dwc3";
|
|
status = "disabled";
|
|
reg = <0x65b00000 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
|
|
dwc3@65a00000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0x65a00000 0x10000>;
|
|
interrupts = <0 134 4>;
|
|
tx-fifo-resize;
|
|
};
|
|
};
|
|
|
|
usb1: usb@65d00000 {
|
|
compatible = "socionext,uniphier-pxs2-dwc3";
|
|
status = "disabled";
|
|
reg = <0x65d00000 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
|
|
dwc3@65c00000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0x65c00000 0x10000>;
|
|
interrupts = <0 137 4>;
|
|
tx-fifo-resize;
|
|
};
|
|
};
|
|
|
|
nand: nand@68000000 {
|
|
compatible = "socionext,uniphier-denali-nand-v5b";
|
|
status = "disabled";
|
|
reg-names = "nand_data", "denali_reg";
|
|
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
|
|
interrupts = <0 65 4>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_nand>;
|
|
clocks = <&sys_clk 2>;
|
|
nand-ecc-strength = <8>;
|
|
};
|
|
};
|
|
};
|
|
|
|
/include/ "uniphier-pinctrl.dtsi"
|