mirror of
https://github.com/brain-hackers/u-boot-brain
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3eafce0527
The local advanced programmable interrupt controller is not used much in U-Boot but we do need to set it up. Add basic support for this, which will be extended as needed. Signed-off-by: Simon Glass <sjg@chromium.org>
60 lines
1.1 KiB
C
60 lines
1.1 KiB
C
/*
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* From Coreboot file of same name
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*
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* Copyright (C) 2014 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef _ARCH_ASM_LAPIC_H
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#define _ARCH_ASM_LAPIC_H
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#include <asm/io.h>
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#include <asm/lapic_def.h>
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#include <asm/msr.h>
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#include <asm/processor.h>
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static inline __attribute__((always_inline))
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unsigned long lapic_read(unsigned long reg)
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{
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return readl(LAPIC_DEFAULT_BASE + reg);
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}
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static inline __attribute__((always_inline))
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void lapic_write(unsigned long reg, unsigned long val)
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{
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writel(val, LAPIC_DEFAULT_BASE + reg);
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}
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static inline __attribute__((always_inline)) void lapic_wait_icr_idle(void)
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{
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do { } while (lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY);
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}
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static inline void enable_lapic(void)
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{
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msr_t msr;
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msr = msr_read(LAPIC_BASE_MSR);
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msr.hi &= 0xffffff00;
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msr.lo &= 0x000007ff;
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msr.lo |= LAPIC_DEFAULT_BASE | (1 << 11);
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msr_write(LAPIC_BASE_MSR, msr);
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}
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static inline void disable_lapic(void)
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{
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msr_t msr;
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msr = msr_read(LAPIC_BASE_MSR);
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msr.lo &= ~(1 << 11);
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msr_write(LAPIC_BASE_MSR, msr);
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}
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static inline __attribute__((always_inline)) unsigned long lapicid(void)
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{
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return lapic_read(LAPIC_ID) >> 24;
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}
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#endif
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