mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-06 04:43:21 +09:00
65dd74a674
Implement SDRAM init using the Memory Reference Code (mrc.bin) provided in the board directory and the SDRAM SPD information in the device tree. This also needs the Intel Management Engine (me.bin) to work. Binary blobs everywhere: so far we have MRC, ME and microcode. SDRAM init works by setting up various parameters and calling the MRC. This in turn does some sort of magic to work out how much memory there is and the timing parameters to use. It also sets up the DRAM controllers. When the MRC returns, we use the information it provides to map out the available memory in U-Boot. U-Boot normally moves itself to the top of RAM. On x86 the RAM is not generally contiguous, and anyway some RAM may be above 4GB which doesn't work in 32-bit mode. So we relocate to the top of the largest block of RAM we can find below 4GB. Memory above 4GB is accessible with special functions (see physmem). It would be possible to build U-Boot in 64-bit mode but this wouldn't necessarily provide any more memory, since the largest block is often below 4GB. Anyway U-Boot doesn't need huge amounts of memory - even a very large ramdisk seldom exceeds 100-200MB. U-Boot has support for booting 64-bit kernels directly so this does not pose a limitation in that area. Also there are probably parts of U-Boot that will not work correctly in 64-bit mode. The MRC is one. There is some work remaining in this area. Since memory init is very slow (over 500ms) it is possible to save the parameters in SPI flash to speed it up next time. Suspend/resume support is not fully implemented, or at least it is not efficient. With this patch, link boots to a prompt. Signed-off-by: Simon Glass <sjg@chromium.org>
110 lines
2.7 KiB
C
110 lines
2.7 KiB
C
/*
|
|
* Copyright (c) 2014 Google, Inc
|
|
*
|
|
* From Coreboot file of the same name
|
|
*
|
|
* Copyright (C) 2007-2008 coresystems GmbH
|
|
* Copyright (C) 2011 Google Inc.
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0
|
|
*/
|
|
|
|
#ifndef _ACH_ASM_SANDYBRIDGE_H
|
|
#define _ACH_ASM_SANDYBRIDGE_H
|
|
|
|
/* Chipset types */
|
|
#define SANDYBRIDGE_MOBILE 0
|
|
#define SANDYBRIDGE_DESKTOP 1
|
|
#define SANDYBRIDGE_SERVER 2
|
|
|
|
/* Device ID for SandyBridge and IvyBridge */
|
|
#define BASE_REV_SNB 0x00
|
|
#define BASE_REV_IVB 0x50
|
|
#define BASE_REV_MASK 0x50
|
|
|
|
/* SandyBridge CPU stepping */
|
|
#define SNB_STEP_D0 (BASE_REV_SNB + 5) /* Also J0 */
|
|
#define SNB_STEP_D1 (BASE_REV_SNB + 6)
|
|
#define SNB_STEP_D2 (BASE_REV_SNB + 7) /* Also J1/Q0 */
|
|
|
|
/* IvyBridge CPU stepping */
|
|
#define IVB_STEP_A0 (BASE_REV_IVB + 0)
|
|
#define IVB_STEP_B0 (BASE_REV_IVB + 2)
|
|
#define IVB_STEP_C0 (BASE_REV_IVB + 4)
|
|
#define IVB_STEP_K0 (BASE_REV_IVB + 5)
|
|
#define IVB_STEP_D0 (BASE_REV_IVB + 6)
|
|
|
|
/* Intel Enhanced Debug region must be 4MB */
|
|
#define IED_SIZE 0x400000
|
|
|
|
/* Northbridge BARs */
|
|
#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */
|
|
#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */
|
|
#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */
|
|
#define DEFAULT_RCBABASE 0xfed1c000
|
|
/* 4 KB per PCIe device */
|
|
#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS
|
|
|
|
/* Device 0:0.0 PCI configuration space (Host Bridge) */
|
|
#define EPBAR 0x40
|
|
#define MCHBAR 0x48
|
|
#define PCIEXBAR 0x60
|
|
#define DMIBAR 0x68
|
|
#define X60BAR 0x60
|
|
|
|
#define GGC 0x50 /* GMCH Graphics Control */
|
|
|
|
#define DEVEN 0x54 /* Device Enable */
|
|
#define DEVEN_PEG60 (1 << 13)
|
|
#define DEVEN_IGD (1 << 4)
|
|
#define DEVEN_PEG10 (1 << 3)
|
|
#define DEVEN_PEG11 (1 << 2)
|
|
#define DEVEN_PEG12 (1 << 1)
|
|
#define DEVEN_HOST (1 << 0)
|
|
|
|
#define PAM0 0x80
|
|
#define PAM1 0x81
|
|
#define PAM2 0x82
|
|
#define PAM3 0x83
|
|
#define PAM4 0x84
|
|
#define PAM5 0x85
|
|
#define PAM6 0x86
|
|
|
|
#define LAC 0x87 /* Legacy Access Control */
|
|
#define SMRAM 0x88 /* System Management RAM Control */
|
|
#define D_OPEN (1 << 6)
|
|
#define D_CLS (1 << 5)
|
|
#define D_LCK (1 << 4)
|
|
#define G_SMRAME (1 << 3)
|
|
#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
|
|
|
|
#define TOM 0xa0
|
|
#define TOUUD 0xa8 /* Top of Upper Usable DRAM */
|
|
#define TSEG 0xb8 /* TSEG base */
|
|
#define TOLUD 0xbc /* Top of Low Used Memory */
|
|
|
|
#define SKPAD 0xdc /* Scratchpad Data */
|
|
|
|
/* Device 0:1.0 PCI configuration space (PCI Express) */
|
|
#define BCTRL1 0x3e /* 16bit */
|
|
|
|
/* Device 0:2.0 PCI configuration space (Graphics Device) */
|
|
|
|
#define MSAC 0x62 /* Multi Size Aperture Control */
|
|
#define SWSCI 0xe8 /* SWSCI enable */
|
|
#define ASLS 0xfc /* OpRegion Base */
|
|
|
|
/*
|
|
* MCHBAR
|
|
*/
|
|
#define MCHBAR_REG(reg) (DEFAULT_RCBA + (reg))
|
|
|
|
#define SSKPD 0x5d14 /* 16bit (scratchpad) */
|
|
#define BIOS_RESET_CPL 0x5da8 /* 8bit */
|
|
|
|
void report_platform_info(void);
|
|
|
|
void sandybridge_early_init(int chipset_type);
|
|
|
|
#endif
|