mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-21 01:18:52 +09:00
100 lines
2.2 KiB
C
100 lines
2.2 KiB
C
/*
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* Copyright (C) 2014 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <malloc.h>
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#include <asm/lapic.h>
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#include <asm/pci.h>
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#include <asm/arch/bd82x6x.h>
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#include <asm/arch/model_206ax.h>
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#include <asm/arch/pch.h>
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#include <asm/arch/sandybridge.h>
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void bd82x6x_pci_init(pci_dev_t dev)
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{
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u16 reg16;
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u8 reg8;
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debug("bd82x6x PCI init.\n");
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/* Enable Bus Master */
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reg16 = pci_read_config16(dev, PCI_COMMAND);
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reg16 |= PCI_COMMAND_MASTER;
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pci_write_config16(dev, PCI_COMMAND, reg16);
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/* This device has no interrupt */
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pci_write_config8(dev, INTR, 0xff);
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/* disable parity error response and SERR */
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reg16 = pci_read_config16(dev, BCTRL);
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reg16 &= ~(1 << 0);
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reg16 &= ~(1 << 1);
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pci_write_config16(dev, BCTRL, reg16);
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/* Master Latency Count must be set to 0x04! */
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reg8 = pci_read_config8(dev, SMLT);
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reg8 &= 0x07;
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reg8 |= (0x04 << 3);
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pci_write_config8(dev, SMLT, reg8);
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/* Will this improve throughput of bus masters? */
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pci_write_config8(dev, PCI_MIN_GNT, 0x06);
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/* Clear errors in status registers */
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reg16 = pci_read_config16(dev, PSTS);
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/* reg16 |= 0xf900; */
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pci_write_config16(dev, PSTS, reg16);
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reg16 = pci_read_config16(dev, SECSTS);
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/* reg16 |= 0xf900; */
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pci_write_config16(dev, SECSTS, reg16);
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}
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#define PCI_BRIDGE_UPDATE_COMMAND
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void bd82x6x_pci_dev_enable_resources(pci_dev_t dev)
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{
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uint16_t command;
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command = pci_read_config16(dev, PCI_COMMAND);
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command |= PCI_COMMAND_IO;
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#ifdef PCI_BRIDGE_UPDATE_COMMAND
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/*
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* If we write to PCI_COMMAND, on some systems this will cause the
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* ROM and APICs to become invisible.
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*/
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debug("%x cmd <- %02x\n", dev, command);
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pci_write_config16(dev, PCI_COMMAND, command);
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#else
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printf("%s cmd <- %02x (NOT WRITTEN!)\n", dev_path(dev), command);
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#endif
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}
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void bd82x6x_pci_bus_enable_resources(pci_dev_t dev)
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{
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uint16_t ctrl;
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ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
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ctrl |= PCI_COMMAND_IO;
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ctrl |= PCI_BRIDGE_CTL_VGA;
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debug("%x bridge ctrl <- %04x\n", dev, ctrl);
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pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
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bd82x6x_pci_dev_enable_resources(dev);
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}
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int bd82x6x_init_pci_devices(void)
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{
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return 0;
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}
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int bd82x6x_init(void)
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{
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bd82x6x_pci_init(PCH_DEV);
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return 0;
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}
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