mirror of
https://github.com/brain-hackers/u-boot-brain
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d7e269cfbd
SPL is using ps7_init.c/h files which are generated from design tools which have to be copied to boards/xilinx/zynq folder before compilation. BSS section is moved to SDRAM because fat support requires more space than SRAM size. Added: - MMC and QSPI support - Boot OS directly from SPL - Enable SPL command Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
59 lines
1.2 KiB
C
59 lines
1.2 KiB
C
/*
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* Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
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* Copyright (C) 2012 Xilinx, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/hardware.h>
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void lowlevel_init(void)
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{
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}
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int arch_cpu_init(void)
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{
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zynq_slcr_unlock();
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#ifndef CONFIG_SPL_BUILD
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/* Device config APB, unlock the PCAP */
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writel(0x757BDF0D, &devcfg_base->unlock);
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writel(0xFFFFFFFF, &devcfg_base->rom_shadow);
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#if (CONFIG_SYS_SDRAM_BASE == 0)
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/* remap DDR to zero, FILTERSTART */
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writel(0, &scu_base->filter_start);
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/* OCM_CFG, Mask out the ROM, map ram into upper addresses */
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writel(0x1F, &slcr_base->ocm_cfg);
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/* FPGA_RST_CTRL, clear resets on AXI fabric ports */
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writel(0x0, &slcr_base->fpga_rst_ctrl);
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/* Set urgent bits with register */
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writel(0x0, &slcr_base->ddr_urgent_sel);
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/* Urgent write, ports S2/S3 */
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writel(0xC, &slcr_base->ddr_urgent);
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#endif
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#endif
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zynq_clk_early_init();
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zynq_slcr_lock();
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return 0;
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}
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void reset_cpu(ulong addr)
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{
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zynq_slcr_cpu_reset();
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while (1)
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;
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}
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#ifndef CONFIG_SYS_DCACHE_OFF
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void enable_caches(void)
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{
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/* Enable D-cache. I-cache is already enabled in start.S */
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dcache_enable();
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}
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#endif
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