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![Simon Goldschmidt](/assets/img/avatar_default.png)
This commit removes ad-hoc reset handling for peripheral resets from SPL for socfpga gen5. This is done because as U-Boot drivers support reset handling by now. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
212 lines
4.9 KiB
C
212 lines
4.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2012 Altera Corporation <www.altera.com>
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/pl310.h>
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#include <asm/u-boot.h>
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#include <asm/utils.h>
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#include <image.h>
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#include <asm/arch/reset_manager.h>
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#include <spl.h>
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#include <asm/arch/system_manager.h>
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#include <asm/arch/freeze_controller.h>
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#include <asm/arch/clock_manager.h>
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#include <asm/arch/misc.h>
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#include <asm/arch/scan_manager.h>
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#include <asm/arch/sdram.h>
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#include <asm/sections.h>
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#include <debug_uart.h>
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#include <fdtdec.h>
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#include <watchdog.h>
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#include <dm/uclass.h>
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DECLARE_GLOBAL_DATA_PTR;
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static struct pl310_regs *const pl310 =
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(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
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static const struct socfpga_system_manager *sysmgr_regs =
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(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
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u32 spl_boot_device(void)
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{
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const u32 bsel = readl(&sysmgr_regs->bootinfo);
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switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
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case 0x1: /* FPGA (HPS2FPGA Bridge) */
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return BOOT_DEVICE_RAM;
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case 0x2: /* NAND Flash (1.8V) */
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case 0x3: /* NAND Flash (3.0V) */
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return BOOT_DEVICE_NAND;
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case 0x4: /* SD/MMC External Transceiver (1.8V) */
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case 0x5: /* SD/MMC Internal Transceiver (3.0V) */
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return BOOT_DEVICE_MMC1;
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case 0x6: /* QSPI Flash (1.8V) */
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case 0x7: /* QSPI Flash (3.0V) */
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return BOOT_DEVICE_SPI;
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default:
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printf("Invalid boot device (bsel=%08x)!\n", bsel);
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hang();
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}
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}
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#ifdef CONFIG_SPL_MMC_SUPPORT
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u32 spl_boot_mode(const u32 boot_device)
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{
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#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
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return MMCSD_MODE_FS;
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#else
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return MMCSD_MODE_RAW;
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#endif
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}
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#endif
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static void socfpga_pl310_clear(void)
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{
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u32 mask = 0xff, ena = 0;
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icache_enable();
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/* Disable the L2 cache */
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clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
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writel(0x111, &pl310->pl310_tag_latency_ctrl);
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writel(0x121, &pl310->pl310_data_latency_ctrl);
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/* enable BRESP, instruction and data prefetch, full line of zeroes */
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setbits_le32(&pl310->pl310_aux_ctrl,
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L310_AUX_CTRL_DATA_PREFETCH_MASK |
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L310_AUX_CTRL_INST_PREFETCH_MASK |
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L310_SHARED_ATT_OVERRIDE_ENABLE);
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/* Enable the L2 cache */
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ena = readl(&pl310->pl310_ctrl);
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ena |= L2X0_CTRL_EN;
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/*
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* Invalidate the PL310 L2 cache. Keep the invalidation code
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* entirely in L1 I-cache to avoid any bus traffic through
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* the L2.
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*/
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asm volatile(
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".align 5 \n"
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" b 3f \n"
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"1: str %1, [%4] \n"
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" dsb \n"
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" isb \n"
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" str %0, [%2] \n"
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" dsb \n"
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" isb \n"
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"2: ldr %0, [%2] \n"
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" cmp %0, #0 \n"
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" bne 2b \n"
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" str %0, [%3] \n"
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" dsb \n"
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" isb \n"
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" b 4f \n"
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"3: b 1b \n"
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"4: nop \n"
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: "+r"(mask), "+r"(ena)
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: "r"(&pl310->pl310_inv_way),
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"r"(&pl310->pl310_cache_sync), "r"(&pl310->pl310_ctrl)
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: "memory", "cc");
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/* Disable the L2 cache */
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clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
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}
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void board_init_f(ulong dummy)
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{
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const struct cm_config *cm_default_cfg = cm_get_default_config();
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unsigned long reg;
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int ret;
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struct udevice *dev;
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/*
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* First C code to run. Clear fake OCRAM ECC first as SBE
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* and DBE might triggered during power on
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*/
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reg = readl(&sysmgr_regs->eccgrp_ocram);
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if (reg & SYSMGR_ECC_OCRAM_SERR)
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writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN,
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&sysmgr_regs->eccgrp_ocram);
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if (reg & SYSMGR_ECC_OCRAM_DERR)
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writel(SYSMGR_ECC_OCRAM_DERR | SYSMGR_ECC_OCRAM_EN,
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&sysmgr_regs->eccgrp_ocram);
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memset(__bss_start, 0, __bss_end - __bss_start);
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socfpga_sdram_remap_zero();
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socfpga_pl310_clear();
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debug("Freezing all I/O banks\n");
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/* freeze all IO banks */
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sys_mgr_frzctrl_freeze_req();
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/* Put everything into reset but L4WD0. */
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socfpga_per_reset_all();
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if (!socfpga_is_booting_from_fpga()) {
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/* Put FPGA bridges into reset too. */
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socfpga_bridges_reset(1);
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}
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socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
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timer_init();
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debug("Reconfigure Clock Manager\n");
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/* reconfigure the PLLs */
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if (cm_basic_init(cm_default_cfg))
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hang();
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/* Enable bootrom to configure IOs. */
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sysmgr_config_warmrstcfgio(1);
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/* configure the IOCSR / IO buffer settings */
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if (scan_mgr_configure_iocsr())
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hang();
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sysmgr_config_warmrstcfgio(0);
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/* configure the pin muxing through system manager */
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sysmgr_config_warmrstcfgio(1);
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sysmgr_pinmux_init();
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sysmgr_config_warmrstcfgio(0);
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/* De-assert reset for bridges based on handoff */
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socfpga_bridges_reset(0);
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debug("Unfreezing/Thaw all I/O banks\n");
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/* unfreeze / thaw all IO banks */
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sys_mgr_frzctrl_thaw_req();
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#ifdef CONFIG_DEBUG_UART
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socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
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debug_uart_init();
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#endif
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ret = spl_early_init();
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if (ret) {
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debug("spl_early_init() failed: %d\n", ret);
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hang();
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}
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ret = uclass_get_device(UCLASS_RESET, 0, &dev);
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if (ret)
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debug("Reset init failed: %d\n", ret);
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/* enable console uart printing */
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preloader_console_init();
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ret = uclass_get_device(UCLASS_RAM, 0, &dev);
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if (ret) {
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debug("DRAM init failed: %d\n", ret);
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hang();
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}
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if (!socfpga_is_booting_from_fpga())
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socfpga_bridges_reset(1);
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}
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