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https://github.com/brain-hackers/u-boot-brain
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bff188baf9
The pixis sgmii command depend on the FPGA support on the board, some 85xx boards support SGMII riser card but did not support this command, define CONFIG_PIXIS_SGMII_CMD for those boards which support the sgmii command. Not like 8544, 8572 has 4 eTsec so that the other two's pixis bits are not supported by 8544. Therefor, define PIXIS_VSPEED2_MASK and PIXIS_VCFGEN1_MASK in header file for both boards. Signed-off-by: Liu Yu <yu.liu@freescale.com>
549 lines
10 KiB
C
549 lines
10 KiB
C
/*
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* Copyright 2006 Freescale Semiconductor
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* Jeff Brown
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* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <watchdog.h>
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#include <asm/cache.h>
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#include <asm/io.h>
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#include "pixis.h"
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static ulong strfractoint(uchar *strptr);
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/*
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* Simple board reset.
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*/
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void pixis_reset(void)
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{
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out8(PIXIS_BASE + PIXIS_RST, 0);
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}
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/*
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* Per table 27, page 58 of MPC8641HPCN spec.
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*/
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int set_px_sysclk(ulong sysclk)
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{
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u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux;
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switch (sysclk) {
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case 33:
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sysclk_s = 0x04;
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sysclk_r = 0x04;
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sysclk_v = 0x07;
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sysclk_aux = 0x00;
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break;
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case 40:
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sysclk_s = 0x01;
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sysclk_r = 0x1F;
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sysclk_v = 0x20;
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sysclk_aux = 0x01;
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break;
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case 50:
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sysclk_s = 0x01;
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sysclk_r = 0x1F;
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sysclk_v = 0x2A;
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sysclk_aux = 0x02;
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break;
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case 66:
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sysclk_s = 0x01;
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sysclk_r = 0x04;
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sysclk_v = 0x04;
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sysclk_aux = 0x03;
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break;
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case 83:
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sysclk_s = 0x01;
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sysclk_r = 0x1F;
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sysclk_v = 0x4B;
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sysclk_aux = 0x04;
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break;
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case 100:
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sysclk_s = 0x01;
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sysclk_r = 0x1F;
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sysclk_v = 0x5C;
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sysclk_aux = 0x05;
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break;
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case 134:
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sysclk_s = 0x06;
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sysclk_r = 0x1F;
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sysclk_v = 0x3B;
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sysclk_aux = 0x06;
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break;
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case 166:
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sysclk_s = 0x06;
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sysclk_r = 0x1F;
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sysclk_v = 0x4B;
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sysclk_aux = 0x07;
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break;
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default:
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printf("Unsupported SYSCLK frequency.\n");
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return 0;
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}
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vclkh = (sysclk_s << 5) | sysclk_r;
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vclkl = sysclk_v;
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out8(PIXIS_BASE + PIXIS_VCLKH, vclkh);
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out8(PIXIS_BASE + PIXIS_VCLKL, vclkl);
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out8(PIXIS_BASE + PIXIS_AUX, sysclk_aux);
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return 1;
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}
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int set_px_mpxpll(ulong mpxpll)
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{
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u8 tmp;
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u8 val;
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switch (mpxpll) {
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case 2:
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case 4:
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case 6:
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case 8:
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case 10:
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case 12:
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case 14:
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case 16:
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val = (u8) mpxpll;
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break;
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default:
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printf("Unsupported MPXPLL ratio.\n");
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return 0;
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}
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tmp = in8(PIXIS_BASE + PIXIS_VSPEED1);
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tmp = (tmp & 0xF0) | (val & 0x0F);
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out8(PIXIS_BASE + PIXIS_VSPEED1, tmp);
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return 1;
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}
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int set_px_corepll(ulong corepll)
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{
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u8 tmp;
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u8 val;
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switch ((int)corepll) {
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case 20:
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val = 0x08;
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break;
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case 25:
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val = 0x0C;
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break;
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case 30:
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val = 0x10;
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break;
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case 35:
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val = 0x1C;
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break;
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case 40:
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val = 0x14;
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break;
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case 45:
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val = 0x0E;
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break;
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default:
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printf("Unsupported COREPLL ratio.\n");
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return 0;
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}
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tmp = in8(PIXIS_BASE + PIXIS_VSPEED0);
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tmp = (tmp & 0xE0) | (val & 0x1F);
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out8(PIXIS_BASE + PIXIS_VSPEED0, tmp);
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return 1;
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}
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void read_from_px_regs(int set)
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{
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u8 mask = 0x1C; /* COREPLL, MPXPLL, SYSCLK controlled by PIXIS */
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u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN0);
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if (set)
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tmp = tmp | mask;
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else
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tmp = tmp & ~mask;
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out8(PIXIS_BASE + PIXIS_VCFGEN0, tmp);
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}
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void read_from_px_regs_altbank(int set)
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{
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u8 mask = 0x04; /* FLASHBANK and FLASHMAP controlled by PIXIS */
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u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN1);
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if (set)
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tmp = tmp | mask;
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else
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tmp = tmp & ~mask;
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out8(PIXIS_BASE + PIXIS_VCFGEN1, tmp);
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}
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#ifndef CONFIG_SYS_PIXIS_VBOOT_MASK
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#define CONFIG_SYS_PIXIS_VBOOT_MASK (0x40)
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#endif
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void clear_altbank(void)
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{
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u8 tmp;
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tmp = in8(PIXIS_BASE + PIXIS_VBOOT);
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tmp &= ~CONFIG_SYS_PIXIS_VBOOT_MASK;
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out8(PIXIS_BASE + PIXIS_VBOOT, tmp);
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}
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void set_altbank(void)
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{
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u8 tmp;
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tmp = in8(PIXIS_BASE + PIXIS_VBOOT);
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tmp |= CONFIG_SYS_PIXIS_VBOOT_MASK;
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out8(PIXIS_BASE + PIXIS_VBOOT, tmp);
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}
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void set_px_go(void)
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{
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u8 tmp;
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tmp = in8(PIXIS_BASE + PIXIS_VCTL);
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tmp = tmp & 0x1E; /* clear GO bit */
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out8(PIXIS_BASE + PIXIS_VCTL, tmp);
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tmp = in8(PIXIS_BASE + PIXIS_VCTL);
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tmp = tmp | 0x01; /* set GO bit - start reset sequencer */
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out8(PIXIS_BASE + PIXIS_VCTL, tmp);
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}
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void set_px_go_with_watchdog(void)
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{
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u8 tmp;
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tmp = in8(PIXIS_BASE + PIXIS_VCTL);
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tmp = tmp & 0x1E;
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out8(PIXIS_BASE + PIXIS_VCTL, tmp);
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tmp = in8(PIXIS_BASE + PIXIS_VCTL);
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tmp = tmp | 0x09;
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out8(PIXIS_BASE + PIXIS_VCTL, tmp);
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}
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int pixis_disable_watchdog_cmd(cmd_tbl_t *cmdtp,
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int flag, int argc, char *argv[])
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{
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u8 tmp;
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tmp = in8(PIXIS_BASE + PIXIS_VCTL);
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tmp = tmp & 0x1E;
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out8(PIXIS_BASE + PIXIS_VCTL, tmp);
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/* setting VCTL[WDEN] to 0 to disable watch dog */
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tmp = in8(PIXIS_BASE + PIXIS_VCTL);
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tmp &= ~0x08;
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out8(PIXIS_BASE + PIXIS_VCTL, tmp);
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return 0;
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}
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U_BOOT_CMD(
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diswd, 1, 0, pixis_disable_watchdog_cmd,
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"diswd - Disable watchdog timer \n",
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NULL);
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#ifdef CONFIG_PIXIS_SGMII_CMD
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int pixis_set_sgmii(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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int which_tsec = -1;
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uchar mask;
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uchar switch_mask;
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if (argc > 2)
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if (strcmp(argv[1], "all") != 0)
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which_tsec = simple_strtoul(argv[1], NULL, 0);
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switch (which_tsec) {
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#ifdef CONFIG_TSEC1
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case 1:
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mask = PIXIS_VSPEED2_TSEC1SER;
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switch_mask = PIXIS_VCFGEN1_TSEC1SER;
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break;
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#endif
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#ifdef CONFIG_TSEC2
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case 2:
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mask = PIXIS_VSPEED2_TSEC2SER;
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switch_mask = PIXIS_VCFGEN1_TSEC2SER;
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break;
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#endif
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#ifdef CONFIG_TSEC3
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case 3:
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mask = PIXIS_VSPEED2_TSEC3SER;
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switch_mask = PIXIS_VCFGEN1_TSEC3SER;
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break;
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#endif
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#ifdef CONFIG_TSEC4
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case 4:
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mask = PIXIS_VSPEED2_TSEC4SER;
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switch_mask = PIXIS_VCFGEN1_TSEC4SER;
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break;
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#endif
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default:
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mask = PIXIS_VSPEED2_MASK;
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switch_mask = PIXIS_VCFGEN1_MASK;
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break;
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}
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/* Toggle whether the switches or FPGA control the settings */
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if (!strcmp(argv[argc - 1], "switch"))
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clrbits_8((unsigned char *)PIXIS_BASE + PIXIS_VCFGEN1,
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switch_mask);
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else
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setbits_8((unsigned char *)PIXIS_BASE + PIXIS_VCFGEN1,
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switch_mask);
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/* If it's not the switches, enable or disable SGMII, as specified */
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if (!strcmp(argv[argc - 1], "on"))
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clrbits_8((unsigned char *)PIXIS_BASE + PIXIS_VSPEED2, mask);
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else if (!strcmp(argv[argc - 1], "off"))
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setbits_8((unsigned char *)PIXIS_BASE + PIXIS_VSPEED2, mask);
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return 0;
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}
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U_BOOT_CMD(
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pixis_set_sgmii, CONFIG_SYS_MAXARGS, 1, pixis_set_sgmii,
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"pixis_set_sgmii"
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" - Enable or disable SGMII mode for a given TSEC \n",
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"\npixis_set_sgmii [TSEC num] <on|off|switch>\n"
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" TSEC num: 1,2,3,4 or 'all'. 'all' is default.\n"
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" on - enables SGMII\n"
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" off - disables SGMII\n"
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" switch - use switch settings\n");
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#endif
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/*
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* This function takes the non-integral cpu:mpx pll ratio
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* and converts it to an integer that can be used to assign
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* FPGA register values.
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* input: strptr i.e. argv[2]
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*/
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static ulong strfractoint(uchar *strptr)
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{
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int i, j, retval;
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int mulconst;
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int intarr_len = 0, decarr_len = 0, no_dec = 0;
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ulong intval = 0, decval = 0;
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uchar intarr[3], decarr[3];
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/* Assign the integer part to intarr[]
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* If there is no decimal point i.e.
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* if the ratio is an integral value
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* simply create the intarr.
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*/
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i = 0;
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while (strptr[i] != '.') {
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if (strptr[i] == 0) {
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no_dec = 1;
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break;
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}
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intarr[i] = strptr[i];
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i++;
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}
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/* Assign length of integer part to intarr_len. */
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intarr_len = i;
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intarr[i] = '\0';
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if (no_dec) {
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/* Currently needed only for single digit corepll ratios */
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mulconst = 10;
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decval = 0;
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} else {
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j = 0;
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i++; /* Skipping the decimal point */
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while ((strptr[i] >= '0') && (strptr[i] <= '9')) {
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decarr[j] = strptr[i];
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i++;
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j++;
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}
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decarr_len = j;
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decarr[j] = '\0';
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mulconst = 1;
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for (i = 0; i < decarr_len; i++)
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mulconst *= 10;
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decval = simple_strtoul((char *)decarr, NULL, 10);
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}
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intval = simple_strtoul((char *)intarr, NULL, 10);
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intval = intval * mulconst;
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retval = intval + decval;
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return retval;
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}
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int
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pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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unsigned int i;
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char *p_cf = NULL;
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char *p_cf_sysclk = NULL;
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char *p_cf_corepll = NULL;
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char *p_cf_mpxpll = NULL;
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char *p_altbank = NULL;
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char *p_wd = NULL;
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unsigned int unknown_param = 0;
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/*
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* No args is a simple reset request.
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*/
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if (argc <= 1) {
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pixis_reset();
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/* not reached */
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}
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for (i = 1; i < argc; i++) {
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if (strcmp(argv[i], "cf") == 0) {
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p_cf = argv[i];
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if (i + 3 >= argc) {
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break;
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}
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p_cf_sysclk = argv[i+1];
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p_cf_corepll = argv[i+2];
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p_cf_mpxpll = argv[i+3];
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i += 3;
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continue;
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}
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if (strcmp(argv[i], "altbank") == 0) {
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p_altbank = argv[i];
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continue;
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}
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if (strcmp(argv[i], "wd") == 0) {
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p_wd = argv[i];
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continue;
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}
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unknown_param = 1;
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}
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/*
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* Check that cf has all required parms
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*/
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if ((p_cf && !(p_cf_sysclk && p_cf_corepll && p_cf_mpxpll))
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|| unknown_param) {
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#ifdef CONFIG_SYS_LONGHELP
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puts(cmdtp->help);
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#endif
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return 1;
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}
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/*
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* PIXIS seems to be sensitive to the ordering of
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* the registers that are touched.
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*/
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read_from_px_regs(0);
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if (p_altbank) {
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read_from_px_regs_altbank(0);
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}
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clear_altbank();
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/*
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* Clock configuration specified.
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*/
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if (p_cf) {
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unsigned long sysclk;
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unsigned long corepll;
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unsigned long mpxpll;
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sysclk = simple_strtoul(p_cf_sysclk, NULL, 10);
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corepll = strfractoint((uchar *) p_cf_corepll);
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mpxpll = simple_strtoul(p_cf_mpxpll, NULL, 10);
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if (!(set_px_sysclk(sysclk)
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&& set_px_corepll(corepll)
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&& set_px_mpxpll(mpxpll))) {
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#ifdef CONFIG_SYS_LONGHELP
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puts(cmdtp->help);
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#endif
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return 1;
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}
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read_from_px_regs(1);
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}
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/*
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* Altbank specified
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*
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* NOTE CHANGE IN BEHAVIOR: previous code would default
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* to enabling watchdog if altbank is specified.
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* Now the watchdog must be enabled explicitly using 'wd'.
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*/
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if (p_altbank) {
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set_altbank();
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read_from_px_regs_altbank(1);
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}
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/*
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* Reset with watchdog specified.
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*/
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if (p_wd) {
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set_px_go_with_watchdog();
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} else {
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set_px_go();
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}
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/*
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* Shouldn't be reached.
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*/
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return 0;
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}
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U_BOOT_CMD(
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pixis_reset, CONFIG_SYS_MAXARGS, 1, pixis_reset_cmd,
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"pixis_reset - Reset the board using the FPGA sequencer\n",
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" pixis_reset\n"
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" pixis_reset [altbank]\n"
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" pixis_reset altbank wd\n"
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" pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
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" pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
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);
|