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https://github.com/brain-hackers/u-boot-brain
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4ddd541d6c
Restructure system manager in the preparation to support A10. No functional change. Change uint32_t to u32. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
42 lines
1.2 KiB
C
42 lines
1.2 KiB
C
/*
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* Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _SYSTEM_MANAGER_H_
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#define _SYSTEM_MANAGER_H_
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#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX (1 << 0)
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#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO (1 << 1)
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#define SYSMGR_ECC_OCRAM_EN (1 << 0)
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#define SYSMGR_ECC_OCRAM_SERR (1 << 3)
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#define SYSMGR_ECC_OCRAM_DERR (1 << 4)
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#define SYSMGR_FPGAINTF_USEFPGA 0x1
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#define SYSMGR_FPGAINTF_SPIM0 (1 << 0)
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#define SYSMGR_FPGAINTF_SPIM1 (1 << 1)
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#define SYSMGR_FPGAINTF_EMAC0 (1 << 2)
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#define SYSMGR_FPGAINTF_EMAC1 (1 << 3)
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#define SYSMGR_FPGAINTF_NAND (1 << 4)
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#define SYSMGR_FPGAINTF_SDMMC (1 << 5)
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#define SYSMGR_SDMMC_DRVSEL_SHIFT 0
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/* EMAC Group Bit definitions */
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#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
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#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
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#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
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#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB 0
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#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB 2
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#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x3
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#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
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#include <asm/arch/system_manager_gen5.h>
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#endif
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#define SYSMGR_GET_BOOTINFO_BSEL(bsel) \
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(((bsel) >> SYSMGR_BOOTINFO_BSEL_SHIFT) & 7)
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#endif /* _SYSTEM_MANAGER_H_ */
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