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https://github.com/brain-hackers/u-boot-brain
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fe3334d0a3
Import misc remaining header files from 2013 U-Boot. These will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
176 lines
6.8 KiB
C
176 lines
6.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020 Marvell International Ltd.
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*/
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#ifndef __CVMX_PKO3_QUEUE_H__
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#define __CVMX_PKO3_QUEUE_H__
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/**
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* @INTERNAL
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*
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* Find or allocate global port/dq map table
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* which is a named table, contains entries for
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* all possible OCI nodes.
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*
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* The table global pointer is stored in core-local variable
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* so that every core will call this function once, on first use.
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*/
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int __cvmx_pko3_dq_table_setup(void);
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/*
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* Get the base Descriptor Queue number for an IPD port on the local node
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*/
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int cvmx_pko3_get_queue_base(int ipd_port);
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/*
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* Get the number of Descriptor Queues assigned for an IPD port
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*/
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int cvmx_pko3_get_queue_num(int ipd_port);
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/**
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* Get L1/Port Queue number assigned to interface port.
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*
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* @param xiface is interface number.
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* @param index is port index.
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*/
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int cvmx_pko3_get_port_queue(int xiface, int index);
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/*
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* Configure L3 through L5 Scheduler Queues and Descriptor Queues
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*
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* The Scheduler Queues in Levels 3 to 5 and Descriptor Queues are
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* configured one-to-one or many-to-one to a single parent Scheduler
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* Queues. The level of the parent SQ is specified in an argument,
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* as well as the number of children to attach to the specific parent.
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* The children can have fair round-robin or priority-based scheduling
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* when multiple children are assigned a single parent.
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*
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* @param node is the OCI node location for the queues to be configured
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* @param parent_level is the level of the parent queue, 2 to 5.
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* @param parent_queue is the number of the parent Scheduler Queue
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* @param child_base is the number of the first child SQ or DQ to assign to
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* @param parent
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* @param child_count is the number of consecutive children to assign
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* @param stat_prio_count is the priority setting for the children L2 SQs
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*
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* If <stat_prio_count> is -1, the Ln children will have equal Round-Robin
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* relationship with eachother. If <stat_prio_count> is 0, all Ln children
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* will be arranged in Weighted-Round-Robin, with the first having the most
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* precedence. If <stat_prio_count> is between 1 and 8, it indicates how
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* many children will have static priority settings (with the first having
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* the most precedence), with the remaining Ln children having WRR scheduling.
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*
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* @returns 0 on success, -1 on failure.
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*
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* Note: this function supports the configuration of node-local unit.
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*/
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int cvmx_pko3_sq_config_children(unsigned int node, unsigned int parent_level,
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unsigned int parent_queue, unsigned int child_base,
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unsigned int child_count, int stat_prio_count);
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/*
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* @INTERNAL
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* Register a range of Descriptor Queues wth an interface port
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*
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* This function poulates the DQ-to-IPD translation table
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* used by the application to retrieve the DQ range (typically ordered
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* by priority) for a given IPD-port, which is either a physical port,
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* or a channel on a channelized interface (i.e. ILK).
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*
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* @param xiface is the physical interface number
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* @param index is either a physical port on an interface
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* @param or a channel of an ILK interface
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* @param dq_base is the first Descriptor Queue number in a consecutive range
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* @param dq_count is the number of consecutive Descriptor Queues leading
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* @param the same channel or port.
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*
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* Only a consecurive range of Descriptor Queues can be associated with any
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* given channel/port, and usually they are ordered from most to least
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* in terms of scheduling priority.
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*
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* Note: thus function only populates the node-local translation table.
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*
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* @returns 0 on success, -1 on failure.
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*/
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int __cvmx_pko3_ipd_dq_register(int xiface, int index, unsigned int dq_base, unsigned int dq_count);
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/**
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* @INTERNAL
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*
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* Unregister DQs associated with CHAN_E (IPD port)
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*/
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int __cvmx_pko3_ipd_dq_unregister(int xiface, int index);
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/*
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* Map channel number in PKO
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*
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* @param node is to specify the node to which this configuration is applied.
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* @param pq_num specifies the Port Queue (i.e. L1) queue number.
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* @param l2_l3_q_num specifies L2/L3 queue number.
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* @param channel specifies the channel number to map to the queue.
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*
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* The channel assignment applies to L2 or L3 Shaper Queues depending
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* on the setting of channel credit level.
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*
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* @return returns none.
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*/
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void cvmx_pko3_map_channel(unsigned int node, unsigned int pq_num, unsigned int l2_l3_q_num,
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u16 channel);
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int cvmx_pko3_pq_config(unsigned int node, unsigned int mac_num, unsigned int pq_num);
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int cvmx_pko3_port_cir_set(unsigned int node, unsigned int pq_num, unsigned long rate_kbips,
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unsigned int burst_bytes, int adj_bytes);
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int cvmx_pko3_dq_cir_set(unsigned int node, unsigned int pq_num, unsigned long rate_kbips,
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unsigned int burst_bytes);
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int cvmx_pko3_dq_pir_set(unsigned int node, unsigned int pq_num, unsigned long rate_kbips,
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unsigned int burst_bytes);
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typedef enum {
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CVMX_PKO3_SHAPE_RED_STALL,
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CVMX_PKO3_SHAPE_RED_DISCARD,
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CVMX_PKO3_SHAPE_RED_PASS
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} red_action_t;
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void cvmx_pko3_dq_red(unsigned int node, unsigned int dq_num, red_action_t red_act,
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int8_t len_adjust);
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/**
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* Macros to deal with short floating point numbers,
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* where unsigned exponent, and an unsigned normalized
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* mantissa are represented each with a defined field width.
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*
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*/
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#define CVMX_SHOFT_MANT_BITS 8
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#define CVMX_SHOFT_EXP_BITS 4
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/**
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* Convert short-float to an unsigned integer
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* Note that it will lose precision.
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*/
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#define CVMX_SHOFT_TO_U64(m, e) \
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((((1ull << CVMX_SHOFT_MANT_BITS) | (m)) << (e)) >> CVMX_SHOFT_MANT_BITS)
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/**
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* Convert to short-float from an unsigned integer
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*/
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#define CVMX_SHOFT_FROM_U64(ui, m, e) \
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do { \
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unsigned long long u; \
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unsigned int k; \
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k = (1ull << (CVMX_SHOFT_MANT_BITS + 1)) - 1; \
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(e) = 0; \
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u = (ui) << CVMX_SHOFT_MANT_BITS; \
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while ((u) > k) { \
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u >>= 1; \
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(e)++; \
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} \
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(m) = u & (k >> 1); \
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} while (0);
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#define CVMX_SHOFT_MAX() \
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CVMX_SHOFT_TO_U64((1 << CVMX_SHOFT_MANT_BITS) - 1, (1 << CVMX_SHOFT_EXP_BITS) - 1)
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#define CVMX_SHOFT_MIN() CVMX_SHOFT_TO_U64(0, 0)
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#endif /* __CVMX_PKO3_QUEUE_H__ */
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