280 lines
7.7 KiB
C
280 lines
7.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020 Marvell International Ltd.
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*/
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#ifndef __CVMX_PCIE_H__
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#define __CVMX_PCIE_H__
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#define CVMX_PCIE_MAX_PORTS 4
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#define CVMX_PCIE_PORTS \
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((OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN73XX)) ? \
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CVMX_PCIE_MAX_PORTS : \
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(OCTEON_IS_MODEL(OCTEON_CN70XX) ? 3 : 2))
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/*
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* The physical memory base mapped by BAR1. 256MB at the end of the
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* first 4GB.
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*/
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#define CVMX_PCIE_BAR1_PHYS_BASE ((1ull << 32) - (1ull << 28))
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#define CVMX_PCIE_BAR1_PHYS_SIZE BIT_ULL(28)
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/*
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* The RC base of BAR1. gen1 has a 39-bit BAR2, gen2 has 41-bit BAR2,
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* place BAR1 so it is the same for both.
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*/
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#define CVMX_PCIE_BAR1_RC_BASE BIT_ULL(41)
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typedef union {
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u64 u64;
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struct {
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u64 upper : 2; /* Normally 2 for XKPHYS */
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u64 reserved_49_61 : 13; /* Must be zero */
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u64 io : 1; /* 1 for IO space access */
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u64 did : 5; /* PCIe DID = 3 */
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u64 subdid : 3; /* PCIe SubDID = 1 */
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u64 reserved_38_39 : 2; /* Must be zero */
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u64 node : 2; /* Numa node number */
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u64 es : 2; /* Endian swap = 1 */
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u64 port : 2; /* PCIe port 0,1 */
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u64 reserved_29_31 : 3; /* Must be zero */
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u64 ty : 1;
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u64 bus : 8;
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u64 dev : 5;
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u64 func : 3;
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u64 reg : 12;
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} config;
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struct {
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u64 upper : 2; /* Normally 2 for XKPHYS */
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u64 reserved_49_61 : 13; /* Must be zero */
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u64 io : 1; /* 1 for IO space access */
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u64 did : 5; /* PCIe DID = 3 */
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u64 subdid : 3; /* PCIe SubDID = 2 */
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u64 reserved_38_39 : 2; /* Must be zero */
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u64 node : 2; /* Numa node number */
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u64 es : 2; /* Endian swap = 1 */
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u64 port : 2; /* PCIe port 0,1 */
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u64 address : 32; /* PCIe IO address */
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} io;
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struct {
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u64 upper : 2; /* Normally 2 for XKPHYS */
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u64 reserved_49_61 : 13; /* Must be zero */
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u64 io : 1; /* 1 for IO space access */
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u64 did : 5; /* PCIe DID = 3 */
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u64 subdid : 3; /* PCIe SubDID = 3-6 */
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u64 reserved_38_39 : 2; /* Must be zero */
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u64 node : 2; /* Numa node number */
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u64 address : 36; /* PCIe Mem address */
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} mem;
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} cvmx_pcie_address_t;
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/**
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* Return the Core virtual base address for PCIe IO access. IOs are
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* read/written as an offset from this address.
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*
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* @param pcie_port PCIe port the IO is for
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*
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* @return 64bit Octeon IO base address for read/write
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*/
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u64 cvmx_pcie_get_io_base_address(int pcie_port);
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/**
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* Size of the IO address region returned at address
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* cvmx_pcie_get_io_base_address()
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*
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* @param pcie_port PCIe port the IO is for
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*
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* @return Size of the IO window
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*/
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u64 cvmx_pcie_get_io_size(int pcie_port);
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/**
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* Return the Core virtual base address for PCIe MEM access. Memory is
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* read/written as an offset from this address.
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*
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* @param pcie_port PCIe port the IO is for
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*
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* @return 64bit Octeon IO base address for read/write
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*/
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u64 cvmx_pcie_get_mem_base_address(int pcie_port);
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/**
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* Size of the Mem address region returned at address
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* cvmx_pcie_get_mem_base_address()
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*
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* @param pcie_port PCIe port the IO is for
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*
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* @return Size of the Mem window
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*/
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u64 cvmx_pcie_get_mem_size(int pcie_port);
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/**
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* Initialize a PCIe port for use in host(RC) mode. It doesn't enumerate the bus.
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*
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* @param pcie_port PCIe port to initialize
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*
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* @return Zero on success
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*/
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int cvmx_pcie_rc_initialize(int pcie_port);
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/**
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* Shutdown a PCIe port and put it in reset
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*
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* @param pcie_port PCIe port to shutdown
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*
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* @return Zero on success
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*/
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int cvmx_pcie_rc_shutdown(int pcie_port);
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/**
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* Read 8bits from a Device's config space
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*
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* @param pcie_port PCIe port the device is on
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* @param bus Sub bus
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* @param dev Device ID
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* @param fn Device sub function
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* @param reg Register to access
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*
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* @return Result of the read
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*/
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u8 cvmx_pcie_config_read8(int pcie_port, int bus, int dev, int fn, int reg);
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/**
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* Read 16bits from a Device's config space
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*
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* @param pcie_port PCIe port the device is on
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* @param bus Sub bus
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* @param dev Device ID
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* @param fn Device sub function
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* @param reg Register to access
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*
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* @return Result of the read
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*/
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u16 cvmx_pcie_config_read16(int pcie_port, int bus, int dev, int fn, int reg);
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/**
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* Read 32bits from a Device's config space
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*
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* @param pcie_port PCIe port the device is on
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* @param bus Sub bus
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* @param dev Device ID
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* @param fn Device sub function
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* @param reg Register to access
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*
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* @return Result of the read
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*/
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u32 cvmx_pcie_config_read32(int pcie_port, int bus, int dev, int fn, int reg);
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/**
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* Write 8bits to a Device's config space
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*
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* @param pcie_port PCIe port the device is on
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* @param bus Sub bus
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* @param dev Device ID
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* @param fn Device sub function
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* @param reg Register to access
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* @param val Value to write
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*/
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void cvmx_pcie_config_write8(int pcie_port, int bus, int dev, int fn, int reg, u8 val);
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/**
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* Write 16bits to a Device's config space
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*
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* @param pcie_port PCIe port the device is on
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* @param bus Sub bus
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* @param dev Device ID
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* @param fn Device sub function
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* @param reg Register to access
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* @param val Value to write
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*/
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void cvmx_pcie_config_write16(int pcie_port, int bus, int dev, int fn, int reg, u16 val);
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/**
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* Write 32bits to a Device's config space
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*
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* @param pcie_port PCIe port the device is on
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* @param bus Sub bus
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* @param dev Device ID
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* @param fn Device sub function
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* @param reg Register to access
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* @param val Value to write
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*/
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void cvmx_pcie_config_write32(int pcie_port, int bus, int dev, int fn, int reg, u32 val);
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/**
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* Read a PCIe config space register indirectly. This is used for
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* registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
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*
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* @param pcie_port PCIe port to read from
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* @param cfg_offset Address to read
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*
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* @return Value read
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*/
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u32 cvmx_pcie_cfgx_read(int pcie_port, u32 cfg_offset);
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u32 cvmx_pcie_cfgx_read_node(int node, int pcie_port, u32 cfg_offset);
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/**
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* Write a PCIe config space register indirectly. This is used for
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* registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
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*
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* @param pcie_port PCIe port to write to
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* @param cfg_offset Address to write
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* @param val Value to write
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*/
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void cvmx_pcie_cfgx_write(int pcie_port, u32 cfg_offset, u32 val);
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void cvmx_pcie_cfgx_write_node(int node, int pcie_port, u32 cfg_offset, u32 val);
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/**
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* Write a 32bit value to the Octeon NPEI register space
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*
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* @param address Address to write to
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* @param val Value to write
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*/
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static inline void cvmx_pcie_npei_write32(u64 address, u32 val)
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{
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cvmx_write64_uint32(address ^ 4, val);
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cvmx_read64_uint32(address ^ 4);
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}
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/**
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* Read a 32bit value from the Octeon NPEI register space
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*
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* @param address Address to read
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* @return The result
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*/
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static inline u32 cvmx_pcie_npei_read32(u64 address)
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{
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return cvmx_read64_uint32(address ^ 4);
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}
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/**
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* Initialize a PCIe port for use in target(EP) mode.
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*
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* @param pcie_port PCIe port to initialize
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*
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* @return Zero on success
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*/
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int cvmx_pcie_ep_initialize(int pcie_port);
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/**
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* Wait for posted PCIe read/writes to reach the other side of
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* the internal PCIe switch. This will insure that core
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* read/writes are posted before anything after this function
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* is called. This may be necessary when writing to memory that
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* will later be read using the DMA/PKT engines.
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*
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* @param pcie_port PCIe port to wait for
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*/
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void cvmx_pcie_wait_for_pending(int pcie_port);
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/**
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* Returns if a PCIe port is in host or target mode.
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*
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* @param pcie_port PCIe port number (PEM number)
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*
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* @return 0 if PCIe port is in target mode, !0 if in host mode.
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*/
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int cvmx_pcie_is_host_mode(int pcie_port);
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#endif
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