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3359eabe03
Import cvmx-l2c-defs.h header file from 2013 U-Boot. It will be used by the later added drivers to support PCIe and networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
173 lines
4.3 KiB
C
173 lines
4.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020 Marvell International Ltd.
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*/
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#ifndef __CVMX_L2C_DEFS_H_
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#define __CVMX_L2C_DEFS_H_
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#define CVMX_L2C_CFG 0x0001180080000000ull
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#define CVMX_L2C_CTL 0x0001180080800000ull
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/*
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* Mapping is done starting from 0x11800.80000000
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* Use _REL for relative mapping
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*/
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#define CVMX_L2C_CTL_REL 0x00800000
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#define CVMX_L2C_BIG_CTL_REL 0x00800030
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#define CVMX_L2C_TADX_INT_REL(i) (0x00a00028 + (((i) & 7) * 0x40000))
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#define CVMX_L2C_MCIX_INT_REL(i) (0x00c00028 + (((i) & 3) * 0x40000))
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/**
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* cvmx_l2c_cfg
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*
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* Specify the RSL base addresses for the block
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*
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* L2C_CFG = L2C Configuration
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*
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* Description:
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*/
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union cvmx_l2c_cfg {
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u64 u64;
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struct cvmx_l2c_cfg_s {
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u64 reserved_20_63 : 44;
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u64 bstrun : 1;
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u64 lbist : 1;
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u64 xor_bank : 1;
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u64 dpres1 : 1;
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u64 dpres0 : 1;
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u64 dfill_dis : 1;
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u64 fpexp : 4;
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u64 fpempty : 1;
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u64 fpen : 1;
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u64 idxalias : 1;
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u64 mwf_crd : 4;
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u64 rsp_arb_mode : 1;
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u64 rfb_arb_mode : 1;
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u64 lrf_arb_mode : 1;
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} s;
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};
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/**
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* cvmx_l2c_ctl
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*
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* L2C_CTL = L2C Control
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*
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*
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* Notes:
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* (1) If MAXVAB is != 0, VAB_THRESH should be less than MAXVAB.
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*
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* (2) L2DFDBE and L2DFSBE allows software to generate L2DSBE, L2DDBE, VBFSBE,
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* and VBFDBE errors for the purposes of testing error handling code. When
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* one (or both) of these bits are set a PL2 which misses in the L2 will fill
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* with the appropriate error in the first 2 OWs of the fill. Software can
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* determine which OW pair gets the error by choosing the desired fill order
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* (address<6:5>). A PL2 which hits in the L2 will not inject any errors.
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* Therefore sending a WBIL2 prior to the PL2 is recommended to make a miss
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* likely (if multiple processors are involved software must be careful to be
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* sure no other processor or IO device can bring the block into the L2).
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*
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* To generate a VBFSBE or VBFDBE, software must first get the cache block
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* into the cache with an error using a PL2 which misses the L2. Then a
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* store partial to a portion of the cache block without the error must
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* change the block to dirty. Then, a subsequent WBL2/WBIL2/victim will
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* trigger the VBFSBE/VBFDBE error.
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*/
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union cvmx_l2c_ctl {
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u64 u64;
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struct cvmx_l2c_ctl_s {
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u64 reserved_29_63 : 35;
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u64 rdf_fast : 1;
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u64 disstgl2i : 1;
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u64 l2dfsbe : 1;
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u64 l2dfdbe : 1;
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u64 discclk : 1;
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u64 maxvab : 4;
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u64 maxlfb : 4;
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u64 rsp_arb_mode : 1;
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u64 xmc_arb_mode : 1;
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u64 reserved_2_13 : 12;
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u64 disecc : 1;
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u64 disidxalias : 1;
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} s;
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struct cvmx_l2c_ctl_cn73xx {
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u64 reserved_32_63 : 32;
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u64 ocla_qos : 3;
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u64 reserved_28_28 : 1;
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u64 disstgl2i : 1;
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u64 reserved_25_26 : 2;
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u64 discclk : 1;
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u64 reserved_16_23 : 8;
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u64 rsp_arb_mode : 1;
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u64 xmc_arb_mode : 1;
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u64 rdf_cnt : 8;
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u64 reserved_4_5 : 2;
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u64 disldwb : 1;
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u64 dissblkdty : 1;
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u64 disecc : 1;
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u64 disidxalias : 1;
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} cn73xx;
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struct cvmx_l2c_ctl_cn73xx cn78xx;
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};
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/**
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* cvmx_l2c_big_ctl
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*
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* L2C_BIG_CTL = L2C Big memory control register
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*
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*
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* Notes:
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* (1) BIGRD interrupts can occur during normal operation as the PP's are
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* allowed to prefetch to non-existent memory locations. Therefore,
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* BIGRD is for informational purposes only.
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*
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* (2) When HOLEWR/BIGWR blocks a store L2C_VER_ID, L2C_VER_PP, L2C_VER_IOB,
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* and L2C_VER_MSC will be loaded just like a store which is blocked by VRTWR.
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* Additionally, L2C_ERR_XMC will be loaded.
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*/
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union cvmx_l2c_big_ctl {
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u64 u64;
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struct cvmx_l2c_big_ctl_s {
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u64 reserved_8_63 : 56;
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u64 maxdram : 4;
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u64 reserved_0_3 : 4;
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} s;
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struct cvmx_l2c_big_ctl_cn61xx {
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u64 reserved_8_63 : 56;
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u64 maxdram : 4;
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u64 reserved_1_3 : 3;
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u64 disable : 1;
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} cn61xx;
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struct cvmx_l2c_big_ctl_cn61xx cn63xx;
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struct cvmx_l2c_big_ctl_cn61xx cn66xx;
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struct cvmx_l2c_big_ctl_cn61xx cn68xx;
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struct cvmx_l2c_big_ctl_cn61xx cn68xxp1;
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struct cvmx_l2c_big_ctl_cn70xx {
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u64 reserved_8_63 : 56;
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u64 maxdram : 4;
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u64 reserved_1_3 : 3;
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u64 disbig : 1;
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} cn70xx;
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struct cvmx_l2c_big_ctl_cn70xx cn70xxp1;
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struct cvmx_l2c_big_ctl_cn70xx cn73xx;
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struct cvmx_l2c_big_ctl_cn70xx cn78xx;
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struct cvmx_l2c_big_ctl_cn70xx cn78xxp1;
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struct cvmx_l2c_big_ctl_cn61xx cnf71xx;
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struct cvmx_l2c_big_ctl_cn70xx cnf75xx;
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};
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struct rlevel_byte_data {
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int delay;
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int loop_total;
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int loop_count;
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int best;
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u64 bm;
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int bmerrs;
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int sqerrs;
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int bestsq;
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};
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#endif
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