710 lines
18 KiB
C
710 lines
18 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020 Marvell International Ltd.
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*
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* Configuration and status register (CSR) type definitions for
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* Octeon asxx.
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*/
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#ifndef __CVMX_ASXX_DEFS_H__
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#define __CVMX_ASXX_DEFS_H__
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#define CVMX_ASXX_GMII_RX_CLK_SET(offset) (0x00011800B0000180ull)
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#define CVMX_ASXX_GMII_RX_DAT_SET(offset) (0x00011800B0000188ull)
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#define CVMX_ASXX_INT_EN(offset) (0x00011800B0000018ull + ((offset) & 1) * 0x8000000ull)
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#define CVMX_ASXX_INT_REG(offset) (0x00011800B0000010ull + ((offset) & 1) * 0x8000000ull)
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#define CVMX_ASXX_MII_RX_DAT_SET(offset) (0x00011800B0000190ull)
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#define CVMX_ASXX_PRT_LOOP(offset) (0x00011800B0000040ull + ((offset) & 1) * 0x8000000ull)
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#define CVMX_ASXX_RLD_BYPASS(offset) (0x00011800B0000248ull + ((offset) & 1) * 0x8000000ull)
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#define CVMX_ASXX_RLD_BYPASS_SETTING(offset) (0x00011800B0000250ull + ((offset) & 1) * 0x8000000ull)
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#define CVMX_ASXX_RLD_COMP(offset) (0x00011800B0000220ull + ((offset) & 1) * 0x8000000ull)
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#define CVMX_ASXX_RLD_DATA_DRV(offset) (0x00011800B0000218ull + ((offset) & 1) * 0x8000000ull)
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#define CVMX_ASXX_RLD_FCRAM_MODE(offset) (0x00011800B0000210ull + ((offset) & 1) * 0x8000000ull)
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#define CVMX_ASXX_RLD_NCTL_STRONG(offset) (0x00011800B0000230ull + ((offset) & 1) * 0x8000000ull)
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#define CVMX_ASXX_RLD_NCTL_WEAK(offset) (0x00011800B0000240ull + ((offset) & 1) * 0x8000000ull)
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#define CVMX_ASXX_RLD_PCTL_STRONG(offset) (0x00011800B0000228ull + ((offset) & 1) * 0x8000000ull)
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#define CVMX_ASXX_RLD_PCTL_WEAK(offset) (0x00011800B0000238ull + ((offset) & 1) * 0x8000000ull)
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#define CVMX_ASXX_RLD_SETTING(offset) (0x00011800B0000258ull + ((offset) & 1) * 0x8000000ull)
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#define CVMX_ASXX_RX_CLK_SETX(offset, block_id) \
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(0x00011800B0000020ull + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)
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#define CVMX_ASXX_RX_PRT_EN(offset) (0x00011800B0000000ull + ((offset) & 1) * 0x8000000ull)
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#define CVMX_ASXX_RX_WOL(offset) (0x00011800B0000100ull + ((offset) & 1) * 0x8000000ull)
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#define CVMX_ASXX_RX_WOL_MSK(offset) (0x00011800B0000108ull + ((offset) & 1) * 0x8000000ull)
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#define CVMX_ASXX_RX_WOL_POWOK(offset) (0x00011800B0000118ull + ((offset) & 1) * 0x8000000ull)
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#define CVMX_ASXX_RX_WOL_SIG(offset) (0x00011800B0000110ull + ((offset) & 1) * 0x8000000ull)
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#define CVMX_ASXX_TX_CLK_SETX(offset, block_id) \
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(0x00011800B0000048ull + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)
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#define CVMX_ASXX_TX_COMP_BYP(offset) (0x00011800B0000068ull + ((offset) & 1) * 0x8000000ull)
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#define CVMX_ASXX_TX_HI_WATERX(offset, block_id) \
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(0x00011800B0000080ull + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)
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#define CVMX_ASXX_TX_PRT_EN(offset) (0x00011800B0000008ull + ((offset) & 1) * 0x8000000ull)
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/**
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* cvmx_asx#_gmii_rx_clk_set
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*
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* ASX_GMII_RX_CLK_SET = GMII Clock delay setting
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*
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*/
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union cvmx_asxx_gmii_rx_clk_set {
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u64 u64;
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struct cvmx_asxx_gmii_rx_clk_set_s {
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u64 reserved_5_63 : 59;
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u64 setting : 5;
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} s;
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struct cvmx_asxx_gmii_rx_clk_set_s cn30xx;
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struct cvmx_asxx_gmii_rx_clk_set_s cn31xx;
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struct cvmx_asxx_gmii_rx_clk_set_s cn50xx;
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};
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typedef union cvmx_asxx_gmii_rx_clk_set cvmx_asxx_gmii_rx_clk_set_t;
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/**
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* cvmx_asx#_gmii_rx_dat_set
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*
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* ASX_GMII_RX_DAT_SET = GMII Clock delay setting
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*
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*/
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union cvmx_asxx_gmii_rx_dat_set {
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u64 u64;
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struct cvmx_asxx_gmii_rx_dat_set_s {
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u64 reserved_5_63 : 59;
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u64 setting : 5;
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} s;
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struct cvmx_asxx_gmii_rx_dat_set_s cn30xx;
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struct cvmx_asxx_gmii_rx_dat_set_s cn31xx;
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struct cvmx_asxx_gmii_rx_dat_set_s cn50xx;
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};
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typedef union cvmx_asxx_gmii_rx_dat_set cvmx_asxx_gmii_rx_dat_set_t;
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/**
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* cvmx_asx#_int_en
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*
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* ASX_INT_EN = Interrupt Enable
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*
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*/
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union cvmx_asxx_int_en {
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u64 u64;
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struct cvmx_asxx_int_en_s {
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u64 reserved_12_63 : 52;
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u64 txpsh : 4;
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u64 txpop : 4;
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u64 ovrflw : 4;
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} s;
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struct cvmx_asxx_int_en_cn30xx {
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u64 reserved_11_63 : 53;
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u64 txpsh : 3;
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u64 reserved_7_7 : 1;
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u64 txpop : 3;
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u64 reserved_3_3 : 1;
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u64 ovrflw : 3;
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} cn30xx;
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struct cvmx_asxx_int_en_cn30xx cn31xx;
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struct cvmx_asxx_int_en_s cn38xx;
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struct cvmx_asxx_int_en_s cn38xxp2;
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struct cvmx_asxx_int_en_cn30xx cn50xx;
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struct cvmx_asxx_int_en_s cn58xx;
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struct cvmx_asxx_int_en_s cn58xxp1;
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};
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typedef union cvmx_asxx_int_en cvmx_asxx_int_en_t;
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/**
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* cvmx_asx#_int_reg
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*
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* ASX_INT_REG = Interrupt Register
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*
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*/
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union cvmx_asxx_int_reg {
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u64 u64;
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struct cvmx_asxx_int_reg_s {
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u64 reserved_12_63 : 52;
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u64 txpsh : 4;
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u64 txpop : 4;
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u64 ovrflw : 4;
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} s;
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struct cvmx_asxx_int_reg_cn30xx {
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u64 reserved_11_63 : 53;
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u64 txpsh : 3;
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u64 reserved_7_7 : 1;
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u64 txpop : 3;
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u64 reserved_3_3 : 1;
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u64 ovrflw : 3;
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} cn30xx;
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struct cvmx_asxx_int_reg_cn30xx cn31xx;
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struct cvmx_asxx_int_reg_s cn38xx;
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struct cvmx_asxx_int_reg_s cn38xxp2;
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struct cvmx_asxx_int_reg_cn30xx cn50xx;
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struct cvmx_asxx_int_reg_s cn58xx;
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struct cvmx_asxx_int_reg_s cn58xxp1;
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};
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typedef union cvmx_asxx_int_reg cvmx_asxx_int_reg_t;
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/**
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* cvmx_asx#_mii_rx_dat_set
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*
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* ASX_MII_RX_DAT_SET = GMII Clock delay setting
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*
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*/
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union cvmx_asxx_mii_rx_dat_set {
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u64 u64;
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struct cvmx_asxx_mii_rx_dat_set_s {
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u64 reserved_5_63 : 59;
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u64 setting : 5;
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} s;
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struct cvmx_asxx_mii_rx_dat_set_s cn30xx;
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struct cvmx_asxx_mii_rx_dat_set_s cn50xx;
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};
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typedef union cvmx_asxx_mii_rx_dat_set cvmx_asxx_mii_rx_dat_set_t;
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/**
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* cvmx_asx#_prt_loop
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*
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* ASX_PRT_LOOP = Internal Loopback mode - TX FIFO output goes into RX FIFO (and maybe pins)
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*
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*/
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union cvmx_asxx_prt_loop {
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u64 u64;
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struct cvmx_asxx_prt_loop_s {
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u64 reserved_8_63 : 56;
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u64 ext_loop : 4;
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u64 int_loop : 4;
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} s;
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struct cvmx_asxx_prt_loop_cn30xx {
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u64 reserved_7_63 : 57;
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u64 ext_loop : 3;
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u64 reserved_3_3 : 1;
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u64 int_loop : 3;
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} cn30xx;
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struct cvmx_asxx_prt_loop_cn30xx cn31xx;
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struct cvmx_asxx_prt_loop_s cn38xx;
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struct cvmx_asxx_prt_loop_s cn38xxp2;
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struct cvmx_asxx_prt_loop_cn30xx cn50xx;
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struct cvmx_asxx_prt_loop_s cn58xx;
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struct cvmx_asxx_prt_loop_s cn58xxp1;
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};
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typedef union cvmx_asxx_prt_loop cvmx_asxx_prt_loop_t;
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/**
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* cvmx_asx#_rld_bypass
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*
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* ASX_RLD_BYPASS
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*
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*/
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union cvmx_asxx_rld_bypass {
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u64 u64;
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struct cvmx_asxx_rld_bypass_s {
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u64 reserved_1_63 : 63;
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u64 bypass : 1;
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} s;
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struct cvmx_asxx_rld_bypass_s cn38xx;
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struct cvmx_asxx_rld_bypass_s cn38xxp2;
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struct cvmx_asxx_rld_bypass_s cn58xx;
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struct cvmx_asxx_rld_bypass_s cn58xxp1;
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};
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typedef union cvmx_asxx_rld_bypass cvmx_asxx_rld_bypass_t;
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/**
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* cvmx_asx#_rld_bypass_setting
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*
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* ASX_RLD_BYPASS_SETTING
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*
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*/
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union cvmx_asxx_rld_bypass_setting {
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u64 u64;
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struct cvmx_asxx_rld_bypass_setting_s {
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u64 reserved_5_63 : 59;
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u64 setting : 5;
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} s;
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struct cvmx_asxx_rld_bypass_setting_s cn38xx;
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struct cvmx_asxx_rld_bypass_setting_s cn38xxp2;
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struct cvmx_asxx_rld_bypass_setting_s cn58xx;
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struct cvmx_asxx_rld_bypass_setting_s cn58xxp1;
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};
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typedef union cvmx_asxx_rld_bypass_setting cvmx_asxx_rld_bypass_setting_t;
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/**
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* cvmx_asx#_rld_comp
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*
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* ASX_RLD_COMP
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*
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*/
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union cvmx_asxx_rld_comp {
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u64 u64;
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struct cvmx_asxx_rld_comp_s {
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u64 reserved_9_63 : 55;
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u64 pctl : 5;
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u64 nctl : 4;
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} s;
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struct cvmx_asxx_rld_comp_cn38xx {
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u64 reserved_8_63 : 56;
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u64 pctl : 4;
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u64 nctl : 4;
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} cn38xx;
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struct cvmx_asxx_rld_comp_cn38xx cn38xxp2;
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struct cvmx_asxx_rld_comp_s cn58xx;
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struct cvmx_asxx_rld_comp_s cn58xxp1;
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};
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typedef union cvmx_asxx_rld_comp cvmx_asxx_rld_comp_t;
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/**
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* cvmx_asx#_rld_data_drv
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*
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* ASX_RLD_DATA_DRV
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*
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*/
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union cvmx_asxx_rld_data_drv {
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u64 u64;
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struct cvmx_asxx_rld_data_drv_s {
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u64 reserved_8_63 : 56;
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u64 pctl : 4;
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u64 nctl : 4;
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} s;
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struct cvmx_asxx_rld_data_drv_s cn38xx;
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struct cvmx_asxx_rld_data_drv_s cn38xxp2;
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struct cvmx_asxx_rld_data_drv_s cn58xx;
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struct cvmx_asxx_rld_data_drv_s cn58xxp1;
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};
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typedef union cvmx_asxx_rld_data_drv cvmx_asxx_rld_data_drv_t;
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/**
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* cvmx_asx#_rld_fcram_mode
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*
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* ASX_RLD_FCRAM_MODE
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*
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*/
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union cvmx_asxx_rld_fcram_mode {
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u64 u64;
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struct cvmx_asxx_rld_fcram_mode_s {
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u64 reserved_1_63 : 63;
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u64 mode : 1;
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} s;
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struct cvmx_asxx_rld_fcram_mode_s cn38xx;
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struct cvmx_asxx_rld_fcram_mode_s cn38xxp2;
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};
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typedef union cvmx_asxx_rld_fcram_mode cvmx_asxx_rld_fcram_mode_t;
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/**
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* cvmx_asx#_rld_nctl_strong
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*
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* ASX_RLD_NCTL_STRONG
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*
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*/
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union cvmx_asxx_rld_nctl_strong {
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u64 u64;
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struct cvmx_asxx_rld_nctl_strong_s {
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u64 reserved_5_63 : 59;
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u64 nctl : 5;
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} s;
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struct cvmx_asxx_rld_nctl_strong_s cn38xx;
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struct cvmx_asxx_rld_nctl_strong_s cn38xxp2;
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struct cvmx_asxx_rld_nctl_strong_s cn58xx;
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struct cvmx_asxx_rld_nctl_strong_s cn58xxp1;
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};
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typedef union cvmx_asxx_rld_nctl_strong cvmx_asxx_rld_nctl_strong_t;
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/**
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* cvmx_asx#_rld_nctl_weak
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*
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* ASX_RLD_NCTL_WEAK
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*
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*/
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union cvmx_asxx_rld_nctl_weak {
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u64 u64;
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struct cvmx_asxx_rld_nctl_weak_s {
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u64 reserved_5_63 : 59;
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u64 nctl : 5;
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} s;
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struct cvmx_asxx_rld_nctl_weak_s cn38xx;
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struct cvmx_asxx_rld_nctl_weak_s cn38xxp2;
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struct cvmx_asxx_rld_nctl_weak_s cn58xx;
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struct cvmx_asxx_rld_nctl_weak_s cn58xxp1;
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};
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typedef union cvmx_asxx_rld_nctl_weak cvmx_asxx_rld_nctl_weak_t;
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/**
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* cvmx_asx#_rld_pctl_strong
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*
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* ASX_RLD_PCTL_STRONG
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*
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*/
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union cvmx_asxx_rld_pctl_strong {
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u64 u64;
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struct cvmx_asxx_rld_pctl_strong_s {
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u64 reserved_5_63 : 59;
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u64 pctl : 5;
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} s;
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struct cvmx_asxx_rld_pctl_strong_s cn38xx;
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struct cvmx_asxx_rld_pctl_strong_s cn38xxp2;
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struct cvmx_asxx_rld_pctl_strong_s cn58xx;
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struct cvmx_asxx_rld_pctl_strong_s cn58xxp1;
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};
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typedef union cvmx_asxx_rld_pctl_strong cvmx_asxx_rld_pctl_strong_t;
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/**
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* cvmx_asx#_rld_pctl_weak
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*
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* ASX_RLD_PCTL_WEAK
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*
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*/
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union cvmx_asxx_rld_pctl_weak {
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u64 u64;
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struct cvmx_asxx_rld_pctl_weak_s {
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u64 reserved_5_63 : 59;
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u64 pctl : 5;
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} s;
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struct cvmx_asxx_rld_pctl_weak_s cn38xx;
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struct cvmx_asxx_rld_pctl_weak_s cn38xxp2;
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struct cvmx_asxx_rld_pctl_weak_s cn58xx;
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struct cvmx_asxx_rld_pctl_weak_s cn58xxp1;
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};
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typedef union cvmx_asxx_rld_pctl_weak cvmx_asxx_rld_pctl_weak_t;
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/**
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* cvmx_asx#_rld_setting
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*
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* ASX_RLD_SETTING
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*
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*/
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union cvmx_asxx_rld_setting {
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u64 u64;
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struct cvmx_asxx_rld_setting_s {
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u64 reserved_13_63 : 51;
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u64 dfaset : 5;
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u64 dfalag : 1;
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u64 dfalead : 1;
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u64 dfalock : 1;
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u64 setting : 5;
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} s;
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struct cvmx_asxx_rld_setting_cn38xx {
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u64 reserved_5_63 : 59;
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u64 setting : 5;
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} cn38xx;
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struct cvmx_asxx_rld_setting_cn38xx cn38xxp2;
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struct cvmx_asxx_rld_setting_s cn58xx;
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struct cvmx_asxx_rld_setting_s cn58xxp1;
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};
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typedef union cvmx_asxx_rld_setting cvmx_asxx_rld_setting_t;
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/**
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* cvmx_asx#_rx_clk_set#
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*
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* ASX_RX_CLK_SET = RGMII Clock delay setting
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*
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*
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* Notes:
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* Setting to place on the open-loop RXC (RGMII receive clk)
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* delay line, which can delay the received clock. This
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* can be used if the board and/or transmitting device
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* has not otherwise delayed the clock.
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*
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* A value of SETTING=0 disables the delay line. The delay
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* line should be disabled unless the transmitter or board
|
|
* does not delay the clock.
|
|
*
|
|
* Note that this delay line provides only a coarse control
|
|
* over the delay. Generally, it can only reliably provide
|
|
* a delay in the range 1.25-2.5ns, which may not be adequate
|
|
* for some system applications.
|
|
*
|
|
* The open loop delay line selects
|
|
* from among a series of tap positions. Each incremental
|
|
* tap position adds a delay of 50ps to 135ps per tap, depending
|
|
* on the chip, its temperature, and the voltage.
|
|
* To achieve from 1.25-2.5ns of delay on the received
|
|
* clock, a fixed value of SETTING=24 may work.
|
|
* For more precision, we recommend the following settings
|
|
* based on the chip voltage:
|
|
*
|
|
* VDD SETTING
|
|
* -----------------------------
|
|
* 1.0 18
|
|
* 1.05 19
|
|
* 1.1 21
|
|
* 1.15 22
|
|
* 1.2 23
|
|
* 1.25 24
|
|
* 1.3 25
|
|
*/
|
|
union cvmx_asxx_rx_clk_setx {
|
|
u64 u64;
|
|
struct cvmx_asxx_rx_clk_setx_s {
|
|
u64 reserved_5_63 : 59;
|
|
u64 setting : 5;
|
|
} s;
|
|
struct cvmx_asxx_rx_clk_setx_s cn30xx;
|
|
struct cvmx_asxx_rx_clk_setx_s cn31xx;
|
|
struct cvmx_asxx_rx_clk_setx_s cn38xx;
|
|
struct cvmx_asxx_rx_clk_setx_s cn38xxp2;
|
|
struct cvmx_asxx_rx_clk_setx_s cn50xx;
|
|
struct cvmx_asxx_rx_clk_setx_s cn58xx;
|
|
struct cvmx_asxx_rx_clk_setx_s cn58xxp1;
|
|
};
|
|
|
|
typedef union cvmx_asxx_rx_clk_setx cvmx_asxx_rx_clk_setx_t;
|
|
|
|
/**
|
|
* cvmx_asx#_rx_prt_en
|
|
*
|
|
* ASX_RX_PRT_EN = RGMII Port Enable
|
|
*
|
|
*/
|
|
union cvmx_asxx_rx_prt_en {
|
|
u64 u64;
|
|
struct cvmx_asxx_rx_prt_en_s {
|
|
u64 reserved_4_63 : 60;
|
|
u64 prt_en : 4;
|
|
} s;
|
|
struct cvmx_asxx_rx_prt_en_cn30xx {
|
|
u64 reserved_3_63 : 61;
|
|
u64 prt_en : 3;
|
|
} cn30xx;
|
|
struct cvmx_asxx_rx_prt_en_cn30xx cn31xx;
|
|
struct cvmx_asxx_rx_prt_en_s cn38xx;
|
|
struct cvmx_asxx_rx_prt_en_s cn38xxp2;
|
|
struct cvmx_asxx_rx_prt_en_cn30xx cn50xx;
|
|
struct cvmx_asxx_rx_prt_en_s cn58xx;
|
|
struct cvmx_asxx_rx_prt_en_s cn58xxp1;
|
|
};
|
|
|
|
typedef union cvmx_asxx_rx_prt_en cvmx_asxx_rx_prt_en_t;
|
|
|
|
/**
|
|
* cvmx_asx#_rx_wol
|
|
*
|
|
* ASX_RX_WOL = RGMII RX Wake on LAN status register
|
|
*
|
|
*/
|
|
union cvmx_asxx_rx_wol {
|
|
u64 u64;
|
|
struct cvmx_asxx_rx_wol_s {
|
|
u64 reserved_2_63 : 62;
|
|
u64 status : 1;
|
|
u64 enable : 1;
|
|
} s;
|
|
struct cvmx_asxx_rx_wol_s cn38xx;
|
|
struct cvmx_asxx_rx_wol_s cn38xxp2;
|
|
};
|
|
|
|
typedef union cvmx_asxx_rx_wol cvmx_asxx_rx_wol_t;
|
|
|
|
/**
|
|
* cvmx_asx#_rx_wol_msk
|
|
*
|
|
* ASX_RX_WOL_MSK = RGMII RX Wake on LAN byte mask
|
|
*
|
|
*/
|
|
union cvmx_asxx_rx_wol_msk {
|
|
u64 u64;
|
|
struct cvmx_asxx_rx_wol_msk_s {
|
|
u64 msk : 64;
|
|
} s;
|
|
struct cvmx_asxx_rx_wol_msk_s cn38xx;
|
|
struct cvmx_asxx_rx_wol_msk_s cn38xxp2;
|
|
};
|
|
|
|
typedef union cvmx_asxx_rx_wol_msk cvmx_asxx_rx_wol_msk_t;
|
|
|
|
/**
|
|
* cvmx_asx#_rx_wol_powok
|
|
*
|
|
* ASX_RX_WOL_POWOK = RGMII RX Wake on LAN Power OK
|
|
*
|
|
*/
|
|
union cvmx_asxx_rx_wol_powok {
|
|
u64 u64;
|
|
struct cvmx_asxx_rx_wol_powok_s {
|
|
u64 reserved_1_63 : 63;
|
|
u64 powerok : 1;
|
|
} s;
|
|
struct cvmx_asxx_rx_wol_powok_s cn38xx;
|
|
struct cvmx_asxx_rx_wol_powok_s cn38xxp2;
|
|
};
|
|
|
|
typedef union cvmx_asxx_rx_wol_powok cvmx_asxx_rx_wol_powok_t;
|
|
|
|
/**
|
|
* cvmx_asx#_rx_wol_sig
|
|
*
|
|
* ASX_RX_WOL_SIG = RGMII RX Wake on LAN CRC signature
|
|
*
|
|
*/
|
|
union cvmx_asxx_rx_wol_sig {
|
|
u64 u64;
|
|
struct cvmx_asxx_rx_wol_sig_s {
|
|
u64 reserved_32_63 : 32;
|
|
u64 sig : 32;
|
|
} s;
|
|
struct cvmx_asxx_rx_wol_sig_s cn38xx;
|
|
struct cvmx_asxx_rx_wol_sig_s cn38xxp2;
|
|
};
|
|
|
|
typedef union cvmx_asxx_rx_wol_sig cvmx_asxx_rx_wol_sig_t;
|
|
|
|
/**
|
|
* cvmx_asx#_tx_clk_set#
|
|
*
|
|
* ASX_TX_CLK_SET = RGMII Clock delay setting
|
|
*
|
|
*
|
|
* Notes:
|
|
* Setting to place on the open-loop TXC (RGMII transmit clk)
|
|
* delay line, which can delay the transmited clock. This
|
|
* can be used if the board and/or transmitting device
|
|
* has not otherwise delayed the clock.
|
|
*
|
|
* A value of SETTING=0 disables the delay line. The delay
|
|
* line should be disabled unless the transmitter or board
|
|
* does not delay the clock.
|
|
*
|
|
* Note that this delay line provides only a coarse control
|
|
* over the delay. Generally, it can only reliably provide
|
|
* a delay in the range 1.25-2.5ns, which may not be adequate
|
|
* for some system applications.
|
|
*
|
|
* The open loop delay line selects
|
|
* from among a series of tap positions. Each incremental
|
|
* tap position adds a delay of 50ps to 135ps per tap, depending
|
|
* on the chip, its temperature, and the voltage.
|
|
* To achieve from 1.25-2.5ns of delay on the received
|
|
* clock, a fixed value of SETTING=24 may work.
|
|
* For more precision, we recommend the following settings
|
|
* based on the chip voltage:
|
|
*
|
|
* VDD SETTING
|
|
* -----------------------------
|
|
* 1.0 18
|
|
* 1.05 19
|
|
* 1.1 21
|
|
* 1.15 22
|
|
* 1.2 23
|
|
* 1.25 24
|
|
* 1.3 25
|
|
*/
|
|
union cvmx_asxx_tx_clk_setx {
|
|
u64 u64;
|
|
struct cvmx_asxx_tx_clk_setx_s {
|
|
u64 reserved_5_63 : 59;
|
|
u64 setting : 5;
|
|
} s;
|
|
struct cvmx_asxx_tx_clk_setx_s cn30xx;
|
|
struct cvmx_asxx_tx_clk_setx_s cn31xx;
|
|
struct cvmx_asxx_tx_clk_setx_s cn38xx;
|
|
struct cvmx_asxx_tx_clk_setx_s cn38xxp2;
|
|
struct cvmx_asxx_tx_clk_setx_s cn50xx;
|
|
struct cvmx_asxx_tx_clk_setx_s cn58xx;
|
|
struct cvmx_asxx_tx_clk_setx_s cn58xxp1;
|
|
};
|
|
|
|
typedef union cvmx_asxx_tx_clk_setx cvmx_asxx_tx_clk_setx_t;
|
|
|
|
/**
|
|
* cvmx_asx#_tx_comp_byp
|
|
*
|
|
* ASX_TX_COMP_BYP = RGMII Clock delay setting
|
|
*
|
|
*/
|
|
union cvmx_asxx_tx_comp_byp {
|
|
u64 u64;
|
|
struct cvmx_asxx_tx_comp_byp_s {
|
|
u64 reserved_0_63 : 64;
|
|
} s;
|
|
struct cvmx_asxx_tx_comp_byp_cn30xx {
|
|
u64 reserved_9_63 : 55;
|
|
u64 bypass : 1;
|
|
u64 pctl : 4;
|
|
u64 nctl : 4;
|
|
} cn30xx;
|
|
struct cvmx_asxx_tx_comp_byp_cn30xx cn31xx;
|
|
struct cvmx_asxx_tx_comp_byp_cn38xx {
|
|
u64 reserved_8_63 : 56;
|
|
u64 pctl : 4;
|
|
u64 nctl : 4;
|
|
} cn38xx;
|
|
struct cvmx_asxx_tx_comp_byp_cn38xx cn38xxp2;
|
|
struct cvmx_asxx_tx_comp_byp_cn50xx {
|
|
u64 reserved_17_63 : 47;
|
|
u64 bypass : 1;
|
|
u64 reserved_13_15 : 3;
|
|
u64 pctl : 5;
|
|
u64 reserved_5_7 : 3;
|
|
u64 nctl : 5;
|
|
} cn50xx;
|
|
struct cvmx_asxx_tx_comp_byp_cn58xx {
|
|
u64 reserved_13_63 : 51;
|
|
u64 pctl : 5;
|
|
u64 reserved_5_7 : 3;
|
|
u64 nctl : 5;
|
|
} cn58xx;
|
|
struct cvmx_asxx_tx_comp_byp_cn58xx cn58xxp1;
|
|
};
|
|
|
|
typedef union cvmx_asxx_tx_comp_byp cvmx_asxx_tx_comp_byp_t;
|
|
|
|
/**
|
|
* cvmx_asx#_tx_hi_water#
|
|
*
|
|
* ASX_TX_HI_WATER = RGMII TX FIFO Hi WaterMark
|
|
*
|
|
*/
|
|
union cvmx_asxx_tx_hi_waterx {
|
|
u64 u64;
|
|
struct cvmx_asxx_tx_hi_waterx_s {
|
|
u64 reserved_4_63 : 60;
|
|
u64 mark : 4;
|
|
} s;
|
|
struct cvmx_asxx_tx_hi_waterx_cn30xx {
|
|
u64 reserved_3_63 : 61;
|
|
u64 mark : 3;
|
|
} cn30xx;
|
|
struct cvmx_asxx_tx_hi_waterx_cn30xx cn31xx;
|
|
struct cvmx_asxx_tx_hi_waterx_s cn38xx;
|
|
struct cvmx_asxx_tx_hi_waterx_s cn38xxp2;
|
|
struct cvmx_asxx_tx_hi_waterx_cn30xx cn50xx;
|
|
struct cvmx_asxx_tx_hi_waterx_s cn58xx;
|
|
struct cvmx_asxx_tx_hi_waterx_s cn58xxp1;
|
|
};
|
|
|
|
typedef union cvmx_asxx_tx_hi_waterx cvmx_asxx_tx_hi_waterx_t;
|
|
|
|
/**
|
|
* cvmx_asx#_tx_prt_en
|
|
*
|
|
* ASX_TX_PRT_EN = RGMII Port Enable
|
|
*
|
|
*/
|
|
union cvmx_asxx_tx_prt_en {
|
|
u64 u64;
|
|
struct cvmx_asxx_tx_prt_en_s {
|
|
u64 reserved_4_63 : 60;
|
|
u64 prt_en : 4;
|
|
} s;
|
|
struct cvmx_asxx_tx_prt_en_cn30xx {
|
|
u64 reserved_3_63 : 61;
|
|
u64 prt_en : 3;
|
|
} cn30xx;
|
|
struct cvmx_asxx_tx_prt_en_cn30xx cn31xx;
|
|
struct cvmx_asxx_tx_prt_en_s cn38xx;
|
|
struct cvmx_asxx_tx_prt_en_s cn38xxp2;
|
|
struct cvmx_asxx_tx_prt_en_cn30xx cn50xx;
|
|
struct cvmx_asxx_tx_prt_en_s cn58xx;
|
|
struct cvmx_asxx_tx_prt_en_s cn58xxp1;
|
|
};
|
|
|
|
typedef union cvmx_asxx_tx_prt_en cvmx_asxx_tx_prt_en_t;
|
|
|
|
#endif
|