272 lines
7.2 KiB
Plaintext
272 lines
7.2 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Marvell / Cavium Inc. CN73xx
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*/
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/dts-v1/;
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#include <dt-bindings/clock/octeon-clock.h>
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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soc0: soc@0 {
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interrupt-parent = <&ciu3>;
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges; /* Direct mapping */
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ciu3: interrupt-controller@1010000000000 {
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compatible = "cavium,octeon-7890-ciu3";
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interrupt-controller;
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/*
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* Interrupts are specified by two parts:
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* 1) Source number (20 significant bits)
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* 2) Trigger type: (4 == level, 1 == edge)
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*/
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <0x10100 0x00000000 0x0 0xb0000000>;
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};
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bootbus: bootbus@1180000000000 {
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compatible = "cavium,octeon-3860-bootbus","simple-bus";
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reg = <0x11800 0x00000000 0x0 0x200>;
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/* The chip select number and offset */
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#address-cells = <2>;
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/* The size of the chip select region */
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#size-cells = <1>;
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};
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clk: clock {
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compatible = "mrvl,octeon-clk";
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#clock-cells = <1>;
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u-boot,dm-pre-reloc;
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};
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gpio: gpio-controller@1070000000800 {
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#gpio-cells = <2>;
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compatible = "cavium,octeon-7890-gpio";
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reg = <0x10700 0x00000800 0x0 0x100>;
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gpio-controller;
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nr-gpios = <32>;
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/* Interrupts are specified by two parts:
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* 1) GPIO pin number (0..15)
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* 2) Triggering (1 - edge rising
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* 2 - edge falling
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* 4 - level active high
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* 8 - level active low)
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*/
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interrupt-controller;
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#interrupt-cells = <2>;
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/* The GPIO pins connect to 16 consecutive CUI bits */
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interrupts = <0x03000 4>, <0x03001 4>,
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<0x03002 4>, <0x03003 4>,
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<0x03004 4>, <0x03005 4>,
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<0x03006 4>, <0x03007 4>,
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<0x03008 4>, <0x03009 4>,
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<0x0300a 4>, <0x0300b 4>,
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<0x0300c 4>, <0x0300d 4>,
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<0x0300e 4>, <0x0300f 4>;
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};
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l2c: l2c@1180080000000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "cavium,octeon-7xxx-l2c";
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reg = <0x11800 0x80000000 0x0 0x01000000>;
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u-boot,dm-pre-reloc;
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};
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lmc: lmc@1180088000000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "cavium,octeon-7xxx-ddr4";
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reg = <0x11800 0x88000000 0x0 0x02000000>; // 2 IFs
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u-boot,dm-pre-reloc;
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l2c-handle = <&l2c>;
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};
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reset: reset@1180006001600 {
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compatible = "mrvl,cn7xxx-rst";
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reg = <0x11800 0x06001600 0x0 0x200>;
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};
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uart0: serial@1180000000800 {
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compatible = "cavium,octeon-3860-uart","ns16550";
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reg = <0x11800 0x00000800 0x0 0x400>;
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clocks = <&clk OCTEON_CLK_IO>;
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clock-frequency = <0>;
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current-speed = <115200>;
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reg-shift = <3>;
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interrupts = <0x08000 4>;
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};
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uart1: serial@1180000000c00 {
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compatible = "cavium,octeon-3860-uart","ns16550";
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reg = <0x11800 0x00000c00 0x0 0x400>;
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clocks = <&clk OCTEON_CLK_IO>;
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clock-frequency = <0>;
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current-speed = <115200>;
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reg-shift = <3>;
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interrupts = <0x08040 4>;
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};
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i2c0: i2c@1180000001000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "cavium,octeon-7890-twsi";
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reg = <0x11800 0x00001000 0x0 0x200>;
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/* INT_ST, INT_TS, INT_CORE */
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interrupts = <0x0b000 1>, <0x0b001 1>, <0x0b002 1>;
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clock-frequency = <100000>;
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clocks = <&clk OCTEON_CLK_IO>;
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};
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i2c1: i2c@1180000001200 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "cavium,octeon-7890-twsi";
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reg = <0x11800 0x00001200 0x0 0x200>;
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/* INT_ST, INT_TS, INT_CORE */
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interrupts = <0x0b100 1>, <0x0b101 1>, <0x0b102 1>;
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clock-frequency = <100000>;
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clocks = <&clk OCTEON_CLK_IO>;
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};
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mmc: mmc@1180000002000 {
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compatible = "cavium,octeon-7890-mmc",
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"cavium,octeon-7360-mmc";
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reg = <0x11800 0x00000000 0x0 0x2100>;
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#address-cells = <1>;
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#size-cells = <0>;
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/* EMM_INT_BUF_DONE,
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EMM_INT_CMD_DONE,
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EMM_INT_DMA_DONE,
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EMM_INT_CMD_ERR,
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EMM_INT_DMA_ERR,
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EMM_INT_SWITCH_DONE,
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EMM_INT_SWITCH_ERR,
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EMM_DMA_DONE,
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EMM_DMA_FIFO*/
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interrupts = <0x09040 1>,
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<0x09041 1>,
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<0x09042 1>,
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<0x09043 1>,
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<0x09044 1>,
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<0x09045 1>,
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<0x09046 1>,
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<0x09000 1>,
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<0x09001 1>;
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clocks = <&clk OCTEON_CLK_IO>;
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};
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spi: spi@1070000001000 {
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compatible = "cavium,octeon-3010-spi";
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reg = <0x10700 0x00001000 0x0 0x100>;
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interrupts = <0x05001 1>;
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#address-cells = <1>;
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#size-cells = <0>;
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spi-max-frequency = <25000000>;
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clocks = <&clk OCTEON_CLK_IO>;
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};
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/* USB 0 */
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usb0: uctl@1180068000000 {
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compatible = "cavium,octeon-7130-usb-uctl";
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reg = <0x11800 0x68000000 0x0 0x100>;
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ranges; /* Direct mapping */
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#address-cells = <2>;
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#size-cells = <2>;
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/* Only 100MHz allowed */
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refclk-frequency = <100000000>;
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/* Only "dlmc_ref_clk0" is supported for 73xx */
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refclk-type-ss = "dlmc_ref_clk0";
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/* Only "dlmc_ref_clk0" is supported for 73xx */
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refclk-type-hs = "dlmc_ref_clk0";
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/*
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* Power is specified by three parts:
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* 1) GPIO handle (must be &gpio)
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* 2) GPIO pin number
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* 3) Active high (0) or active low (1)
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*/
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xhci@1680000000000 {
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compatible = "cavium,octeon-7130-xhci","synopsys,dwc3","snps,dwc3";
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reg = <0x16800 0x00000000 0x10 0x0>;
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interrupts = <0x68080 4>; /* UAHC_IMAN, level */
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maximum-speed = "super-speed";
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dr_mode = "host";
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snps,dis_u3_susphy_quirk;
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snps,dis_u2_susphy_quirk;
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snps,dis_enblslpm_quirk;
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};
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};
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/* USB 1 */
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usb1: uctl@1180069000000 {
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compatible = "cavium,octeon-7130-usb-uctl";
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reg = <0x11800 0x69000000 0x0 0x100>;
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ranges; /* Direct mapping */
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#address-cells = <2>;
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#size-cells = <2>;
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/* 50MHz, 100MHz and 125MHz allowed */
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refclk-frequency = <100000000>;
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/* Either "dlmc_ref_clk0" or "dlmc_ref_clk0" */
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refclk-type-ss = "dlmc_ref_clk0";
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/* Either "dlmc_ref_clk0" "dlmc_ref_clk1" or "pll_ref_clk" */
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refclk-type-hs = "dlmc_ref_clk0";
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/*
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* Power is specified by three parts:
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* 1) GPIO handle (must be &gpio)
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* 2) GPIO pin number
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* 3) Active high (0) or active low (1)
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*/
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xhci@1690000000000 {
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compatible = "cavium,octeon-7130-xhci","synopsys,dwc3","snps,dwc3";
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reg = <0x16900 0x00000000 0x10 0x0>;
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interrupts = <0x69080 4>; /* UAHC_IMAN, level */
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dr_mode = "host";
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};
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};
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/* PCIe 0 */
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pcie0: pcie@1180069000000 {
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compatible = "marvell,pcie-host-octeon";
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reg = <0 0xf2600000 0 0x10000>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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dma-coherent;
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bus-range = <0 0xff>;
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marvell,pcie-port = <0>;
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ranges = <0x81000000 0x00000000 0xd0000000 0x00011a00 0xd0000000 0x00000000 0x01000000 /* IO */
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0x02000000 0x00000000 0xe0000000 0x00011b00 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */
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0x43000000 0x00011c00 0x00000000 0x00011c00 0x00000000 0x00000010 0x00000000>;/* prefetchable memory */
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};
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uctl@118006c000000 {
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compatible = "cavium,octeon-7130-sata-uctl", "simple-bus";
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reg = <0x11800 0x6c000000 0x0 0x100>;
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ranges; /* Direct mapping */
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#address-cells = <2>;
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#size-cells = <2>;
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portmap = <0x3>;
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staggered-spinup;
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cavium,qlm-trim = "4,sata";
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sata: sata@16c0000000000 {
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compatible = "cavium,octeon-7130-ahci";
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reg = <0x16c00 0x00000000 0x0 0x200>;
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#address-cells = <2>;
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#size-cells = <2>;
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interrupts = <0x6c010 4>;
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};
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};
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};
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};
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